US6709404
"Referring now to the drawings in detail wherein like numerals refer to like elements throughout the several views, one sees that FIG. 1 is an exploded plan view of pharyngometer 10 of the present invention."
US6397117
"An exemplary embodiment of the invention is described hereinafter, by way of example only（単なる例示）, with reference to the accompanying drawings in which like reference signs relate to like parts and in which:"
US5204497
"Other Objects of the present invention and many of the attendant advantages of the present invention will be readily appreciated as the same becomes better understood by reference to the following detailed description when considered in connection with the accompanying drawings, in which like reference numerals designate like parts throughout the figures thereof and wherein:"
US20060272020
"In the following drawings, like reference numerals designate like or similar parts throughout the drawings."
US20090164605
"[0011] The present invention is illustrated by way of example, and not by way of limitation（非限定）, in the figures of the accompanying drawings and in which like reference numerals refer to similar elements."
US781332
" In FIG. 3, wherein like reference numerals are used for corresponding elements of all other figures, there are shown two SSP capable central offices 13 and 17 which may be located in the same or different states and regions."
US7080132
"The present invention is illustrated by way of example and not limited by the figures of the accompanying drawings in which like references indicate similar elements and in which:"
US7054928
"In the drawings wherein like reference characters denote similar elements throughout the several views:"
US20070293195
"[0021] Accompanied drawings are part of the description and useful for illustrating embodiments of the present invention and for explaining the principle of the present invention together with the description, wherein like reference signs represent the same or similar elements."
US7430633
"FIGS. 1-5 describe various embodiments in connection with devices, systems and/or architectures. These figures include common components and for sake of brevity as the discussion through the respective figures progresses infra, redundant description（冗長な説明）of already described components is omitted for sake of brevity（簡潔、理解の容易のため省略）."
US20150087307
"Repetitive description of like elements employed in respective embodiments of systems and/or apparatus described herein are omitted for sake of brevity（簡潔さのため省略）."
US20140103582
"[0019] The engaging parameters of the controllable particle beam 102 for the purposes of opening up the hole 11 may include particle beam intensity, beam diameter, duration of the engaging, and possibly others."
US7321118
"Because the ion source used with the microscope disclosed herein can achieve sub-nanometer beam diameter, the microscope of the invention can achieve that which was previously possible only with an electron beam."
US7880151
"Next, as shown in FIG. 2, a focused ion beam using a high beam current with a correspondingly large beam size is used to mill rectangles 202 and 204, respectively in front of and behind the region of interest, leaving a thin vertical sample section, lamella 206, that includes a vertical cross section of the area of interest."
US6292503
"The lateral resolution can be about the electron beam size because of the small thin film specimen that has been formed, using the focused ion beam device."
beam diameterの方が多いかも。
US8713777
"It is noted that in the present embodiment as shown, the end plate 116 and the body 104, is actually composed of two separate parts which are pressed together. However, this is not to be taken as a limitation, and it is presently preferred that the body 104 and the end plate 116 be a single unitary member."
US4363603
"It will therefore be understood that while a preferred embodiment of the invention has been shown and described, this is not to be taken as a limitation on its scope which is more properly described by the following claims."
US20080216488
"[0040] While the invention has been disclosed in connection with certain preferred embodiments, this should not be taken as a limitation to all of the provided details. Modifications and variations of the described embodiments may be made without departing from the spirit and scope of the invention, and other embodiments should be understood to be encompassed in the present disclosure as would be understood by those of ordinary skill in the art."
US7550870
"This should not be taken to limit the invention, which, using the teachings provided herein, can be applied to other situations, such as cable television networks, wireless networks, etc."
US4224285
"It will be appreciated that the structure of a smoke filter unit, according to this invention, is quite simple and consequently low cost in its construction. While particular embodiments of the invention have been described above in considerable detail, this is not to be taken as in any way limiting the invention but merely as being descriptive thereof."
US6108703
" In this illustrative embodiment, the inventive framework 35 is deployed by an Internet Service Provider (ISP), although this is not a limitation of the present invention."
US6368311
"Although FIGS. 9-11 illustrate the two flat surfaces on either side of the partitions 107 as being spaced differently from the cover member 101, this is not a limitation."
US7779510
"It is to be understood that other embodiments may be utilized and structural or logical changes may be made without departing from the scope of the present invention. Therefore, the following detailed description is not to be taken in a limiting sense, and the scope of the present invention is defined by the appended claims and their equivalents."
US4614762
"The following examples are given for illustrative purposes only and are not meant to be a limitation on the invention as defined in the appended claims. All parts and percentages are by weight unless otherwise indicated."
US7891731
"However, the number of positioning elements is not meant to be a limitation of the present invention."
US5116654
"Of course, these frequencies have been designated by convention, and are not meant to be restrictive."
US6980390
"The servo layer may include an organic material where the indicia are created in the servo layer with an infrared or ultra violet light source such that the indicia are formed embedded（埋め込まれて）within the tape."
US7951697
"In accordance with another embodiment illustrated by the dashed lines, circuit pattern 3852 is formed embedded（埋め込まれて）within lower surface 616L of dielectric material 616A."
US8507783
"In this embodiment of an interior surface (embedded portion) of saddle body 1000, further co-planar negative circuit layer (e.g., conductive laminate) connections 1332 are formed embedded（埋め込まれて）within the saddle body to connect with cavity roof portions of alternating cavities 220."
US6533949
"According to a further feature of the present invention, a plurality of connecting holes are formed penetrating（貫通して）into a face of the wafer opposite to the projections"
formed so as to ...の方が良いか？
US6468830
"Semiconductor chips are connected to（接続）external circuitry through electrical contacts on a front face（上面）of the chip. Each contact on the chip must be connected to external circuitry, such as the circuitry of a supporting substrate or circuit panel. Various processes for making these interconnections（接続）use prefabricated arrays of leads or discrete（個別）wires. For example, in the so-called tape automated bonding or “TAB” process, a dielectric supporting tape, such as a thin foil of polyimide includes an array of metallic leads on one surface of the dielectric film. These leads are aligned with the contacts on the front face of the chip. The dielectric film is juxtaposed with（並置、並列）the chip so that the leads extend（延在）over the front or contact bearing（設ける、配設、載置）surface on the chip. The leads are then bonded to（接合）the contacts of the chip, as by ultrasonic or thermocompression bonding. The terminals on the dielectric film may then be connected to external circuitry for electrically interconnecting the chip and the external circuitry.
The rapid evolution（進歩、進化）of the semiconductor art（技術）in recent years has created a continued demand for semiconductor chip packages having progressively（一層）greater numbers of contacts and leads in a given amount of space. An individual（個々、一個）chip may require hundreds or even thousands of contacts, all within the area of the front face of the chip. Certain complex semiconductor chips currently being used have contacts spaced apart from（離間）one another at center-to-center（中心間）distances of 0.1 mm or less and, in some cases, 0.05 mm or less. With such closelyspaced contacts the leads connected to the chip contacts must be extremely fine structures, typically having a smaller bonded surface than the contacts onto which they are bonded so that the adjacent leads do not electrically short（短絡）. Such fine（微細、微小）structures are susceptible to（受け易い、しやすい、容易）damage and deformation."
"Leads are typically bonded to contacts on a semiconductor chip or other microelectronic element using ultrasonic, thermocompression or thermosonic bonding. In the bonding process, the bonding region of each lead is engaged（係合）by a bonding tool which bears on（押し付け、載置）the top surface of the lead in the bonding region and forces the lead downwardly into engagement with the contact. Energy supplied through the bonding tool causes the bonding metal to join with（接合、結合）the contact. Typically, the leads are bonded to the chip contacts with the bonding tool using heat, force, ultrasonic energy, or a combination of two or more thereof（それらの2つ以上の組み合わせ）, for a given time period. If incorrect force, heat and/or ultrasonic energy is used, the bond（接合部）between the leads and the contacts may be too weak to withstand thermal cycling stresses during operation of the chip (heating and cooling cycles during operation). Also, the bonding tool may create areas of the lead which are prone to early fatigue during thermal cycling because of excessive non-uniform deformations in the bonding region typically causing early breaks in the lead at the point the lead bends up from the chip surface (commonly referred to as a “heel break”)."
US7118389
"A socket for solderless connection between a stud-bumped（スタッドバンプ）IC chip and a host PCB. The socket includes a three-dimensional (e.g., cylindrical or cubical（立方体) hollow metal frame that is either free-standing（自立）or supported by an underlying（下方、下部）patterned template structure. The metal frame includes side walls（側壁）that extend（延在）away from the host PCB, and a contact structure located at the upper (i.e., free) end of the side walls. The contact structure defines an opening through which a stud bump can be inserted into a central chamber of the metal frame. The side walls and/or the contact structure are formed such that when the tip end（先端）of the stud bump is inserted into the central chamber, at least one of the base structure and the sidewall（少なくとも一方）of the stud bump abuts（当接）the contact structure at two or more contact points."
abut (vi): to touch along a border or with a projecting part; terminate at a point of contact; lean or rest for support (Merriam-Webster Unabrided)
"1. A socket for electrically connecting a stud bump mounted thereon, the stud bump including a base section and an elongated（長い、長尺）body extending between the base section to a tip end, ... the contact structure defining an opening that communicates with（連通）the central chamber..."
"Recently, the stud-bump bonding (SBB) technology, which is based on the wire-bonding technology, has been developed（開発）as a very attractive solution（手法、手段）for a low-cost flip-chip technology. With SBB technology, gold stud bumps are placed on the die bond pads of IC chips through a modification of the “ball bonding” process used in conventional wire bonding. In ball bonding, the tip（先端）of the gold bond wire is melted to form a sphere. The wire-bonding tool presses this sphere against（押し付け）the aluminum bond pad, applying mechanical force, heat, and ultrasonic energy to create a metallic connection. The wire-bonding tool next extends the gold wire to the connection pad on the board, substrate, or lead frame, and makes a “stitch” bond to that pad, finishing by breaking off（切断）the bond wire to begin another cycle. For gold stud bumping, the first ball bond is made as described, but the wire is then broken close above the ball. The resulting gold ball with truncated wire, or “stud bump”, remains on the bond pad to provide（して～を可能とする）a permanent, reliable connection through the aluminum oxide to the underlying metal. This technology has several advantages: UBM process is not necessary, bumping cost is low, and fine-pitch（狭い、微小ピッチ） and chip-level bumping is possible."
Staking（かしめ継ぎ、加締め）, Wikipedia
"Staking is the process of connecting two components by creating an interference fit between the two pieces. One workpiece has a hole in it while the other has a boss that fits within the hole. The boss is very slightly undersized so that it forms a slip fit. A staking punch is then used to expand the boss radially and to compress the boss axially so as to form an interference fit between the workpieces. This forms a permanent joint.[1]"
Swaging（スエージング、据込み加工）, Wikipedia
"Swaging ... is a forging process in which the dimensions of an item are altered using dies into which the item is forced.[1] Swaging is usually a cold working process; however, it is sometimes done as a hot working process.[2]
The term swage can apply to the process of swaging (verb), or to a die or tool used for swaging (noun)."
プレス金型講座（ミスミ）
超音波機器加工事例（日本アビオニクス株式会社）
US6492715
"One known method for manufacturing multiple layer thin film interposers is by dispersing a first layer of polyimide on a carrier plate, typically composed of（から成る）glass, forming vias, or micro-holes through this polyamide dielectric layer in a predetermined patterns, and then depositing copper or other conductive wire leads thereon by sputtering, plating, or other known methods."
"Copper, or other conductive material, is then dispersed on the layer of thin film and patterned into circuitry through sputtering, plating, etching, or other known process."
US6738240
"Ni—Fe or other Permalloy materials which can be easily formed through sputtering are preferred, although other materials with analogous（類似、同様）properties may work as well."
"The insulating material used for the insulating layers mentioned above（上述）is preferably an inorganic compound such as silicon oxide (for example SiO2 produced（作る、得る）by sputtering or CVD or PECVD, and SiO by evaporation) or silicon nitride."
US6895645
"One reported fabrication of MEMS thin and thick film bimorphs is by depositing piezoelectric thin or thick films on both sides of a metal plate or foil through sputtering or hydrothermal growth processes."
"The piezoelectric thin films, usually PZT, for such uses are made by sol-gel, sputtering, laser ablation, chemical vapor deposition or other appropriate process."
"Once those elements requiring polishing and/or cleaning have been addressed, electrodes are deposited on the surface of the elements 56 by techniques such as sputtering or evaporation with a shadow mask."
US6020243
"Referring to FIG. 6, a metal layer 32 (e.g. zirconium) is deposited directly on surface 28, e.g. by sputtering, evaporation, chemical vapor deposition (CVD) or plasma CVD."
"Copper pennies are useful in demonstrating the concept of copper plating. A simple lemon bath is used to demonstrate this process. Lemon juice is a natural acid that attacks the oxidized copper-oxygen bond, releasing it from the surface of the pennies. Placement of a metal such as an iron nail in the lemon bath containing suspended copper ions results in a simple copper plating of the iron nail."(Copper plating, Wikipedia)
本当かな～？
US6051888
"FIG. 1 is an exploded view of the present invention showing a flip-chip package 10. Semiconductor device 12 is mounted on substrate 11 which is used to interconnect the various electrical connections 22 (FIG. 2) of semiconductor device 12 to a mounting surface（搭載面、実装面、取付面）, for example a printed wiring board."
US8629566
"Note that resistor 50 can be erected in tomb-stone fashion（墓石のように）(with its longest dimension perpendicular to the mounting surface（搭載面) as shown by dotted line 51 to reduce the area (or “foot print”（設置面積）) needed for the substrate 10."
US5399898
"In another embodiment, the first semiconductor die is a double-sided flip-chip die, the substrate has conductive pads disposed on a mounting surface（搭載面）thereof, and the first semiconductor die is mounted to（取付）the conductive pads on the substrate."
Flip Chip, Wikipedia
"Flip chip, also known as controlled collapse chip connection or its abbreviation, C4,[1] is a method for interconnecting（接続、相互接続）semiconductor devices, such as IC chips and microelectromechanical systems (MEMS), to external circuitry（外部回路）with solder bumps that have been deposited onto（堆積？）the chip pads. The solder bumps are deposited on the chip pads on the top side（上面）of the wafer during the final wafer processing step. In order to mount（実装、取付）the chip to external circuitry (e.g., a circuit board or another chip or wafer), it is flipped over so that its top side faces down（下を向く）, and aligned so that its pads align with（整合、一致）matching（対応する）pads on the external circuit, and then the solder is reflowed to complete the interconnect. This is in contrast to wire bonding, in which the chip is mounted upright（正立）and wires are used to interconnect the chip pads to external circuitry.[2]"
Wire bonding/thermosonic bonding[edit]
In typical semiconductor fabrication systems chips are built up in large numbers（多数、大量に）on a single large wafer of（から成る）semiconductor material, typically silicon. The individual chips are patterned with small pads of metal near their edges that serve as the connections（接続部）to an eventual mechanical carrier. The chips are then cut out of the wafer and attached to their carriers, typically via wire bonding such as Thermosonic Bonding. These wires eventually lead to（つながる、結合）pins on the outside of the carriers, which are attached to the rest of the circuitry making up（構成）the electronic system.
US6828220
"BACKGROUND OF THE INVENTION
This invention relates to leadframe-based packages and, more particularly, to flip chip interconnection（フリップチップ接続）to the leadframe.
Leadframe-based packages are used extensively（広く）in electronic packaging due to their low cost. The first level interconnection is typically achieved through wire bonding. Recent demands for improved electrical performance, particularly for devices used in RF applications, has led to（必要性から～に至る）consideration of “flip chip” interconnection to the leadframe.
Conventional flip chip devices employ solder bumps to make contact between the die and the bonding fingers of the leadframe. Devices based on solder bumps have not been accepted for many applications, because of high cost and because the process of soldering bumps to leadframes presents technical challenges（技術的に困難）, such as solder run-out. What is needed is（必要、求め）a package configuration that accomplishes flip chip interconnection to the leadframe but which retains the low cost of conventional leadframe-based packaging."
"1. A method for connecting a die to a leadframe, comprising: forming metal bumps on the die, contacting（接触させる）the bumps with bonding fingers on a leadframe, heating the bumps without melting, and pressing the bumps against the bonding fingers,
wherein the heating step and the pressing step are carried out（実行、行う）at a temperature and pressure sufficient to result in deformation of the bump material to an extent of（程度）between about 15% and about 20% of the original bump height.
2. The method of claim 1 wherein the step of forming the metal bumps comprises（含む）stud bumping.
3. The method of claim 1 wherein the step of forming the metal bumps comprises electroplating.
4. The method of claim 1 wherein the metal bumps comprise（から成る）gold."
"Generally, a flip chip-in-leadframe package according to the invention may have a “leaded”（リード付き）footprint（設置面積？）or configuration, or a “leadless” configuration; and, where the device has a leadless configuration, the leads or bonding fingers may “fan outwardly” or “fan inwardly”. Moreover, the die may be situated “cavity-upward” or “cavity-downward”. Each arrangement provides advantages according to the particular application. The various configurations may be more fully understood by reference to the Figs. and to the description, following, referring thereto."
"Turning now to the Figs., a flip chip-in-leadframe package 10 according to the invention is shown diagrammatically in a plan view（平面図）in FIG. 1 and in a sectional elevational view（立断面図）in FIG. 2, having a leaded footprint in which the leads fan outwardly（外側に広がる）. The package 10 includes a die 12 having die bumps 14, and leadframes 16. Die 12 is attached by way of（介して）die bumps 14 to bonding fingers 22 of leadframes 16. In the embodiment shown in FIGS. 1 and 2 the die and bumps and portions of the leadframes are enclosed in a plastic body 18, leaving the ends 20 of the leads exposed at the periphery for connection.
The die bumps can be formed by any of a variety of（様々）techniques, including techniques well known in the art. The die bumps preferably（好適）are formed by a technique such as gold stud bumping and electroplating. The bumps preferably are formed by a gold stud-bumping technique, an operation similar to wire bonding."
"The invention is particularly useful in construction of flip chip-in-leadframe packages having any of a variety of leadless（リード無し）footprints. For example, FIG. 3 shows a cavity-down leadless package construction generally at 30（参照番号30で）in which the die bumps 36 are peripherally（周縁に）located, while the leadframe 38 lands 39 for attachment of solder balls 37 for connection of the package are centrally（中央部に）located."
US7215011
"1. A semiconductor die package comprising: a leadframe; a die that includes a backside（裏面）, wherein the backside of the die forms a first electrical terminal; solder coupling a frontside（表面）of the die to the leadframe, wherein the frontside of the die comprises（有する）a second electrical terminal, and wherein the first electrical terminal and the second electrical terminal are terminals in a MOSFET device; and a body including an encapsulating（封入、封止）material that encapsulates the die such that the backside of the die is adjacent to a window defined within the body, wherein the leadframe has leads and wherein ends（端部）of the leads of the leadframe are substantially coplanar（同一平面上、面一）with the backside of the die."
"2. Description of the Prior Art
In power transistor packages, those in the art are generally still using chip and wire bond interconnect technology. It is difficult to simplify the manufacturing process flow as all process steps, such as, for example, die attach, wire bond, and molding are required. As a result, there is a limit placed on（限界、限度がある）the maximum size for the die. Thus（従って）, power transistor packages are suited for single die applications since formation of an isolated metal pad for power transistor packages that include multiple dies is very difficult.
Recent attempts to improve packaging of chip devices have included directly coupling lead frames to the die. However, this technology does not lend itself well to（向いてない、利用は容易でない）the manufacture of thinner outline (or profile) packages. Hence（その結果、従って）, such packages, as well as those using wire bond interconnect technology, tend to be thick."
"The present invention provides a chip device that includes a leadframe including a plurality of leads and a die coupled to（結合、接続）the leadframe. The die includes a metallized back side（裏面）as well as source and gate terminals opposite（対向、反対）the metallized backside. The die is coupled to the leadframe such that the leads of the leadframe are directly coupled to the terminals. The chip device also includes a body including a window defined therein. The body is placed around at least a portion of the leadframe and the die such that the metallized back side of the die is adjacent the window."
US7511939
(Abstract)
"A layered（積層）capacitor structure comprises two or more semiconductor/dielectric plates formed above an insulating surface which provides mechanical support, with the plates arranged（配設、配置）in a vertical stack（積層体）on the insulating surface. An insulating layer is on each plate, patterned and etched to provide an opening which allows the top of one plate to be in physical and electrical contact with the bottom of the subsequent plate. Contact openings are provided through the insulating layers, each of which provides access to a respective（それぞれ、各々）semiconductor layer and is insulated from any other（その他）semiconductor/dielectric plate. Electrical contacts through the contact openings provide（得られる、もたらす、可能とする）electrical connections to respective semiconductor layers. The present structure can include as many stacked layers（層の積み重ね）as needed to provide a desired total capacitance or range of capacitances."
"1. Field of the Invention
This invention relates generally to integrated circuit (IC) capacitors, and more particularly to a layered capacitor architecture and fabrication method.
2. Description of the Related Art
Integrated circuits（＊無冠詞複数、一般）frequently require the use of one or more capacitive devices, which serve numerous purposes in both analog and digital circuits. For example, a capacitor（＊不定冠詞、具体例）can provide an integration function, serve as part of a filter design, act as an energy or data storage device, or provide a bypass or decoupling capacitance on an IC.
However, a capacitor integrated on an IC die is necessarily（必然的）small, and thus inherently（元来、本質的、避けられない）limited with respect to the amount of capacitance it can provide. At the same time, modern electronic circuits require devices with ever greater（より大きな）capacitances. However, as integration density（＊無冠詞）increases, chip space（＊無冠詞）for large capacitors is less readily available. Numerous capacitor designs are known for providing increased capacitance by increasing the area of their conductive plates, and/or reducing the thickness of their dielectric layer. However, these devices remain limited（依然として、未だに、まだ限定）in their ability to provide high capacitance values, due to the limited chip area typically allotted for capacitors.
Off-chip devices can provide large capacitances, but often cannot be used due to their size, as well as the length and number of connections required and the attendant signal propagation times, resistive voltage drops and connection inductances.
SUMMARY OF THE INVENTION
A layered capacitor architecture and fabrication method are presented（提供）which enables a designer to provide a relatively high capacitance in a limited amount of chip area.
The structure of the present integrated circuit capacitor structure is fabricated（作製）on an insulating surface which provides mechanical support. Two or more semiconductor/dielectric plates are arranged in a vertical stack on top of the insulating surface, each of which comprises a first semiconductor layer and a dielectric layer on the semiconductor layer, the semiconductor and dielectric layers patterned and etched such that they have a desired pattern, and such that（＊such thatの繰り返し）each pair of semiconductor layers separated by a dielectric layer form a capacitor. The structure also includes a topmost（最上位）layer which forms a capacitor with the topmost semiconductor/dielectric plate.
An insulating layer is deposited on each semiconductor/dielectric plate, and is patterned and etched to provide an opening such that the semiconductor layer of the plate immediately above the insulating layer is in physical and electrical contact with the dielectric layer of the plate immediately below the insulating layer.
After all plates have been formed, contact openings are made（設ける）through the insulating layers, each of which provides access to a respective semiconductor layer. The structure is arranged such that each contact opening provides access to one semiconductor layer, and is insulated from all other semiconductor/dielectric plates. Electrical contacts are provided through the contact openings and to the topmost layer to provide electrical connections to respective semiconductor layers.
Stacking（重ねる、積層）two capacitors in this way essentially reduces the required die area by 50% in comparison with a comparably-sized（同等）conventional capacitor. The present structure can include as many stacked layers as needed to provide a desired total capacitance or range of capacitances. In this way, total area consumed by a capacitor on a given integrated circuit is reduced in comparison with a comparably-sized conventional capacitor.
These and other features, aspects, and advantages of the present invention will become better understood with reference to the following drawings, description, and claims.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1is schematic diagram illustrating the layered capacitor architecture of the present invention.
FIGS. 2a and 2 b（＊図番の英字が小文字）are sectional and corresponding plan views of a layered capacitor per the present invention.
FIGS. 3a-14 a are sectional views illustrating a method of fabricating a layered capacitor per（従う）the present invention."
US7857886
"The present invention relates to laminated ceramic capacitors（積層セラミックコンデンサ）also known as multi layered ceramic chip capacitors (MLCC)（積層セラミックコンデンサ；村田製作所）, and particularly to the internal electrode material used in the fabrication of such capacitors.
Multi layered ceramic chip capacitors generally consist of（から成る）a dielectric ceramic matrix with embedded metal sheet electrodes of some μm（数ミクロン）thickness and some 10 μm of distance. In manufacturing such capacitors, suitable pastes of powdered ceramic matrix precursor material and suitable pastes of a metal powder are alternatively laminated（積層）on each other. Sometimes there is also provided a thin intermediate material. After lamination（積層）the laminate（積層体）is dried and heated to about 300 to 450° C. (normally under air（空気下（空気中？）) to decompose the organic binder of the pastes. Thereafter the laminate is further heated under vacuum or inert gas atmosphere（雰囲気下で）to about 1000 to 1350° C., mostly to at least 1200° C., for sintering（焼結）and formation of the ceramic dielectric material."
「養液土耕（ようえきどこう）とは、灌水同時施肥栽培のことである」(Wikipedia)
Irrigation & Fertilization = Fertigation (Irrigation and fertilization in hydroponics, PDF)
「潅水同時施肥は...fertigationに相当する」「野菜の省力・低コスト栽培技術」
drip fertigation （日本養液栽培研究会）
Electromagnetic coil, Wikipedia
An electromagnetic coil is an electrical conductor such as a wire in the shape of（形状）a coil, spiral or helix.[1][2] Electromagnetic coils are used in electrical engineering, in applications where electric currents interact with magnetic fields, in devices such as inductors, electromagnets, transformers, and sensor coils. Either an electric current is passed through（通す、流す）the wire of the coil to generate a magnetic field, or conversely an external time-varying（時間とともに変化、時変）magnetic field through the interior of the coil generates an EMF (voltage) in the conductor.
A current through any conductor creates a circular magnetic field（＊不定冠詞）around the conductor due to Ampere's law.[3] The advantage of using the coil shape is that it increases the strength of magnetic field（＊無冠詞）produced by a given current. The magnetic fields（＊定冠詞＋複数）generated by the separate turns of wire（個別の巻線により発生された磁界）all pass through the center of the coil and add（合成、足す、加算）(superpose) to produce a strong field there.[3] The more turns of wire, the stronger the field produced. Conversely, a changing external magnetic flux induces a voltage in a conductor such as a wire, due to Faraday's law of induction.[3][4] The induced voltage can be increased by winding the wire into a coil, because the field lines intersect the circuit multiple times.[3]
The direction of the magnetic field produced by a coil can be determined by the right hand grip rule（右手の法則）. If the fingers of the right hand are wrapped around the magnetic core of a coil in the direction of conventional current through the wire, the thumb will point in the direction the magnetic field lines pass through the coil. The end of a magnetic core from which the field lines emerge is defined to be the North pole.
The wire or conductor which constitutes the coil is called the winding（巻線）.[5] The hole in the center of the coil is called the core area or magnetic axis.[6] Each loop of wire（電線、ワイヤ）is called a turn（巻き？、ターン）.[2] In windings in which the turns touch, the wire must be insulated with a coating of nonconductive insulation such as plastic or enamel to prevent the current from passing between the wire turns. The winding is often wrapped around a coil form made of plastic or other material to hold it in place（固定、保持）.[2] The ends（端部）of the wire are brought out（取り出す、引き出す）and attached to an external circuit. Windings may have additional electrical connections along their length; these are called taps.[7] A winding which has a single tap in the center of its length is called center-tapped.[8]
