ENGLISH LANGUAGE & USAGE
The Difference Between
perimeter: 外周、周長（数学）、周辺、外面
periphery: 周辺、外面
Merriam Webster Unabridgedによれば、peripheryは1) the perimeter of a circle, ellipse, or other closed curvilinear figure, 2) the external boundary or surface of any body
peripheryにすでにexternalの意味があるから、例えば「外周部」の訳としてexternal (outer) periphery portionは冗長か？
追記 内周があれば別
threadedly：実例少ない？
US6874764
"1. A mechanical jack comprising: first and second housing members telescopically（伸縮、入れ子）moveable relative to each other; a jack screw having a threaded（ねじを切る、螺装）surface and a disruption（途絶？）at one end, the jack screw extending within the first and second housing members; and a stroke limiting nut comprising: a nut wall; a substantially circular interior surface at least a portion of which is threaded so as to threadedly engage（螺合）the jack screw; and a screw travel（移動、移動量）limiting surface located at a distal end（先端、末端）of said nut that engages the disruption to limit travel of the jack screw."
US6271467
"As may be seen in FIGS. 2 and 5 the flange 16 is provided with a plurality of holes 16a around its periphery（周辺、外縁、周縁）for receiving screws 24 which extend therethrough and threadedly engage（螺合）the adjacent wall of the transformer T."
US7089772
(Abstract)
"An adjustable horn or mandrel for a spiral pipe forming machine（＊体言止め）. Such machines are made（作る、作製）for continuously forming metal pipe from an elongated（長い、長尺）sheet of metal where the sheet is curled into adjacent helical convolutions in a multiple roll pipe forming head. The head includes a mandrel, and in accordance with the invention a mandrel mount（マウント、取付け部）is provided for vertical adjustment of the mandrel. The mandrel mount has opposite side supports sandwiching（挟む、挟持）the mandrel and a motor mounted for raising and lowering the mandrel between the side supports. Raising and lowering is accomplished（達成）via a pair lead screws secured to the mandrel, each having a gear threadedly engaged（螺合）thereon and which is driven by the motor. The mandrel is also horizontally adjustable."
US8087977
"Traditionally, in some grinders, the grinder wheel was held in place（固定）on the wheel spindle by two flanges, one on each side of the grinder wheel. Typically, the upper flange was slidingly（摺動）received on the wheel spindle while the lower flange was threadingly（螺合）received on the wheel spindle. As the grinders were used, the threadedly（螺合）attached flange had a tendency to over-tighten."
"The truncated annular portion 182 slideably receives the upper flange 184 and the threaded portion 184 threadingly（螺合）receives lower flange 186."
"In a preferred embodiment, at least a portion of the through-bore 210 is threaded for threaded engagement（螺合）with the threaded portion 184 of wheel spindle 34."
US7921928
"A lock nut 28 can be threadedly engaged（螺合）with the horizontal segment 22 of the outer housing 20 and can be disposed against the sprinkler body 12."
US5649765
"An angled mixing screw transmission shaft, angled at approximately 107° with respect to the vertical, engages（係合）the vertical mixing screw drive shaft."
英字新聞の記事(INYT, JUNE25-26, 2016, page2)より：
"I asked Trump if it was harder to flip politicians or the real estate people he has dealt with over the years."
「トランプに、政治家を弾き飛ばすのと、これまで付き合ってきた不動産業者を弾き飛ばすのは、どちらが簡単だったかと聞いた」
同じ内容を和英翻訳するとすると、元の、if（かどうか）を使った英語は出てきそうにない。
I asked Trump which was harder, to flip politicians or the real estate people.
それか、せいぜいwhetherだろう。
I asked Trump whether it was harder to flip politicians or the real estate people.
でも、慣れれば何てことないのかも知れない。
US5122818
"Molded plastic packages are widely used to house microelectronic devices, such as silicon based semiconductor integrated circuits. The molded plastic packages are characterized by low cost, ease of assembly and adequate protection of the device from water vapor and other sources of corrosion. Usually, the device is mounted on a centrally positioned die attach paddle. The electronic device is then electrically interconnected（相互接続）to the inner ends of a plurality of leads which approach（接近）the die attach paddle from at least one side and up to all four sides of the paddle. Electrical interconnection is typically by wire bonding or tape automated bonding. Following electrical interconnection, the centrally positioned die attach paddle, electronic device and inner portion of the leadframe are encapsulated（封入）in a molding resin by a process such as transfer molding. The resin forms a hard, relatively moisture impervious（耐湿性、通さない）shell protecting both the semiconductor device and the electrical connections."
US8053869
(Abstract)
"A package (10) includes an integrated circuit device (12) having an electrically active surface (16) and an opposing（反対）backside surface (14). A dielectric molding resin（モールド樹脂）(26) at least partially encapsulates（封入、封止）the integrated circuit die and the plurality of electrically conductive leads (20) with the backside surface（裏面）(14) and the plurality of electrical contacts (24) being exposed on opposing sides of the package (10). Features（形状）(30) are formed into electrically inactive portions of the integrated circuit die (12) to seal（封止）moisture paths and relieve packaging stress. The features (30) are formed by forming a trough (54) partially through the backside (56) of the wafer (40) in alignment with（揃う、一致、合致）a saw street (48), the trough (54) having a first width; and forming a channel (62) extending from the trough (54) to the electrically active face (42) to thereby singulate（単体化）the integrated circuit device member, the channel (62) having a second width that is less than the first width."
"Molded plastic electronic packages provide environmental protection to integrated circuit devices. Packages such as the PQFP (plastic quad flat pack) and the PLCC (plastic leaded chip carrier) protect an encapsulated（封入）device from contaminants such as moisture and from mechanical shock.
One disadvantage with molded plastic packages is poor thermal dissipation（放熱）. During operation, the integrated circuit device generates heat that must be removed to maintain the operating integrity of the device. Some heat is dissipated（放熱）through the bonding wires and the lead frame, the remainder is absorbed into the molding resin. The molding resin is a poor thermal conductor so the device temperature increases. To prevent the device from overheating, the power provided to the device must be limited."
US6188130
"Molded plastic electronic packages provide environmental protection to integrated circuit devices. Packages such as the QFP (quad flat package) and PLCC (plastic-leaded chip carrier) protect an encapsulated device from contaminants such as moisture as well as from mechanical shock. One molded plastic package is illustrated in U.S. Pat. No. 4,707,724 to Suzuki et al. The package has a leadframe with a centrally positioned die attach pad. The semiconductor device is bonded to（接合）the pad and electrically interconnected（接続）to the inner ends of the leadframe. A polymer molding resin encapsulates（封入）the device, die attach pad and inner lead ends.
One disadvantage with molded plastic packages is poor thermal dissipation. During operation, the semiconductor device generates heat which must be removed to maintain the operating integrity of the device. While some heat is dissipated through the bonding wires and leadframe, the remainder is absorbed into the molding resin. The molding resin is a poor thermal conductor so the device temperature will increase unless the power provided to the device is limited.
Incorporating a heat spreader into the molded plastic package provides an enhanced path for thermal dissipation. As a result, more power may be provided to the semiconductor device without a resultant excessive increase in device temperature. The heat spreader, which is usually copper or aluminum, is embedded in the molding resin, usually below the die attach pad, reducing the amount of molding resin through which heat must pass to reach a surface of the package."
US7816186
"In lead frame based semiconductor packages, electrical signals are transmitted between at least one integrated circuit device (die) and external circuitry, such as a printed circuit board, by an electrically conductive（導電性）lead frame. The lead frame includes a number of leads, each having an inner lead end and an opposing（反対の）outer lead frame end. The inner lead ends are electrically interconnected to input/output (I/O) pads on the die and the outer lead ends provide terminals outside the package body for interconnection to external circuitry. When the outer lead end terminates at（終わる、終端）a sidewall of the package body, the package is known as a "no lead" package. If the outer leads extend beyond the package body perimeter（外周）, the package is referred to as "leaded." Examples of well known no-lead packages include quad flat no lead (QFN) packages which have four sets of leads disposed around the perimeter of the bottom of a square package body and dual flat no lead (DFN) packages which have two sets of lead disposed along opposite（反対）sides of the bottom of a package body."
"If a flat package bottom is desired, additional molding resin, or another dielectric, may be utilized to seal（封止）the cut areas."
US7148083
"Integrated circuitry chips are typically formed into packages, with the packages then being mounted or otherwise connected to other substrates and devices. Many different packaging methods and devices exist for integrated circuitry in the form of a semiconductor chip. One exemplary package mounts a semiconductor chip to another circuit substrate, for example a printed circuit board. The printed circuit board is typically fabricated to have a plurality of conductive traces formed thereon in desired patterns. An insulative layer referred to as a soldermask is then typically formed on the circuit substrate. Such layers are typically patterned to provide openings to locations on the circuit traces therebeneath（その下）. The soldermask typically prevents solder bridging（橋絡？）on the circuit side of the assembly. The semiconductor chip is typically mounted to the circuit substrate by being adhered to（接着）the soldermask with a die attach adhesive. Conductive wire or other bonding is then conducted to connect the circuitry of the chip with the circuitry of the substrate.
Thereafter, in one exemplary packaging process, an insulative encapsulant material（封入材）is provided to one side of the substrate over the semiconductor chip and soldermask. Such can be formed by a transfer molding process whereby（というプロセス）a mold having a void is placed against the circuit substrate and an encapsulant（封入材、剤）caused to flow therein. The mold is ultimately（最終的）removed and the encapsulant is allowed to cure."
"Traditionally, soldermask materials are used to cover all areas of a ball grid array substrate that are not specifically open to reveal some part of the underlying circuit. In the area of the perimeter of the mold body, the soldermask is typically used to protect the circuit traces from the clamping forces applied by the mold body and to form a level surface of the ball grid array substrate so that the mold body can form a good seal（封止状態）during encapsulation."
US7381606
"The trade-off between （兼ね合い、トレードオフ）the on-state voltage drop and turn-off losses is commonly done in power devices by adjusting the lifetime of the charge carriers in the whole of the drift layer. This however tends to reduce severely the charge in the whole of the n-drift layer leading to a poor trade-off between on-state losses and switching losses."
US6740912
"To this end, the relatively complex processing sequences needed to form LDD structures, which are considered a necessary trade-off （犠牲、代償）in conventional short channel length devices, are unnecessary in the present invention."
US4458287
"In prior devices, without the noted nonsymmetrical leakage characteristics, one must tolerate the trade-off between protective shunting and phase control accuracy in AC gate applications."
US8022447
"The energy filter can be "tuned" in terms of certain characteristics, including energetic width and position, in order to achieve a desired trade-off between high on-state current and low off-state leakage (and steep inverse subthreshold slope) in the device."
US7015054
"their light transmission characteristics tend to trade-off against （犠牲にする）electrical operating efficiency"
"These conditions result in a trade-off between series resistance and light extraction efficiency and serve to limit the electrical-to-optical power conversion efficiency of the LED."
US5684390
"There is a trade-off between performance and reject rate."
Fip chip, Wikipedia
"Flip chip, also known as controlled collapse chip connection or its abbreviation, C4,[1] is a method for interconnecting semiconductor devices, such as IC chips and microelectromechanical systems (MEMS), to external circuitry with（用いて）solder bumps that have been deposited onto（堆積）the chip pads. The solder bumps are deposited on the chip pads on the top side of the wafer during the final wafer processing step. In order to mount（搭載）the chip to external circuitry (e.g., a circuit board or another chip or wafer), it is flipped over so that its top side faces down, and aligned so that its pads align with（一致、整列）matching（対応）pads on the external circuit, and then the solder is reflowed（リフロー）to complete the interconnect（相互接続）. This is in contrast to wire bonding, in which the chip is mounted upright and wires are used to interconnect the chip pads to external circuitry."
US5583378
"In well region 236, integrated circuit chip 202 is surrounded by interconnection substrate 208. Interconnection substrate 208 is a multi-layer printed circuit board laminate（積層体）. Insulating layers 214 can be made of（作る、作製）prepreg layers created（作製、得る）with bizmaleimide triazine (BT) resin materials using printed circuit board fabrication methods well known to those of skill in the art. BT prepreg layers are available from Mitsubishi Gas and Chemical Company of Japan. Conductive trace layers 212 are created by methods well known to those of skill in the art such as photo lithography, etching, and black oxide treatment（黒化処理）of thin layers of copper. Insulating layers 214 and conductive trace layers 212 are laminated（積層）together with epoxy resin (not shown). Conductive vias or plated through holes 220 can then be drilled, or laser ablated（除去）, and plated to form conductors for electrical connections between the various conductive trace layers 212."
Laser ablation, Wikipedia
disperse（分散？）
split
spectrally separate?
separate into spectral components?
subject to spectroscopy?
US9110291
(Abstract)
"Methods and apparatus for combining（結合）or separating spectral components（スペクトル成分を分光？分散？）by means of a polychromat. A polychromat is employed to combine a plurality of beams, each derived from a separate source, into a single output beam, thereby providing for definition of one or more of the intensity, color, color uniformity, divergence angle, degree of collimation, polarization, focus, or beam waist of the output beam. The combination of sources and polychromat may serve（働く、機能、作用）as an enhanced-privacy display and to multiplex signals of multiple spectral components. In other embodiments of the invention, a polychromat serves to disperse spectral components for spectroscopic or de-multiplexing applications."
WO2009101374
(Abstract)
"Method and apparatus for detecting, by absorption spectroscopy（吸光分光法）, an isotopic ratio of a sample, by passing（通す）first and second laser beams of different frequencies through the sample. Two IR absorption cells are used, a first containing a reference gas of known isotopic ratio and the second containing a sample of unknown isotopic ratio. An interlacer or reflective chopper may be used so that as the laser frequencies are scanned the absorption of the sample cell and the reference cell are detected alternately. This ensures that（することができる、可能にする）the apparatus is continuously calibrated and rejects the baseline noise when phase sensitive detection is used."
US20030020010
"[0057] A laser beam 760 generated by a laser and optical system as known in the art enters（入射）the vacuum chamber 720 via a central opening 770 in the front wall 750a during operation of the TOF-MS array instrument 700. The laser beam 760 is split（分光？）into multiple beams. Each beam is then directed by optics, e.g., mirrors and lenses, through a central axis of a corresponding TOF-MS 710 to simultaneously activate all the TOF-MSs 710. The laser and optical system is preferably a diode pumped Ni-YAG laser system capable of producing short laser pulses and tightly focused beams for minute sample interrogation.
[0058] The acquired time-of-flight data from the array is parallel processed（並列処理）by data acquisition and analysis hardware having a plurality of parallel processors (i.e., arrayed transient digitizers) and software modules designed for acquiring and processing the data. First, the acquired data corresponding to a respective TOF-MS 710 of the plurality of TOF-MSs 710 is provided to a corresponding processor of the plurality of parallel processors. Second, the acquired data corresponding to each of the plurality of TOF-MSs 710 is simultaneously processed by the plurality of parallel processors."
US6928311
"1. A measuring device for non-invasively measuring levels of constituents in blood and tissue in a subject, the measuring device comprising: (a) a housing having an opening for receiving a hand of the subject; (b) a polychromatic light source that emits a broad spectrum of light in the near infrared range and adjacent visible light; (c) a part receptor shaped（形、形状）for receiving a finger of the subject, the part receptor being located（＊分詞）relative to the light source so that when the finger of the subject is placed in the part receptor, the light source can be activated and light from the light source can be directed onto the finger, the part receptor being shaped to receive the finger in close alignment, so as to reduce extraneous light; (d) a light receptor for collecting a continuum of wavelengths over the broad spectrum of light after the broad spectrum of light has been directed onto the finger; (e) a dispersion（分散、分光？）element coupled to the light receptor for dispersing（分光？）light collected by the light receptor into a dispersed spectrum of component wavelengths; (f) a photodetector coupled to the dispersion element for taking absorbance measurements（測定値を得る）from the dispersed spectrum and producing a measurement signal; (g) a communications interface connectable to an external computer for communicating（伝達、送る）the measurement signal to the external computer, and (h) a power interface connectable to an external stabilized power source."
US6522618
"An integrated optical apparatus includes an optically transparent substrate with a light source and a detector mounted adjacent thereto. The substrate includes an optical element in a transmit path from the light source to a remote target. The optical element splits（分光？）the light into more than one beam. A detector receives beams reflected by the target. All optical elements needed to create the more then one beam, direct the more than one beam onto the target and direct the more than one beam from the target to the detector are on the substrate and/or any structure bonded to the substrate.
ある回路から別の回路への「回り込み信号」
wrap-around signal ?
runaround signal ?
stray signal ?
sneak signal ?
extraneous signal ?
US20080002793
"[0029] FIG. 2 is a schematic block diagram depicting a full duplex device enabled with a digital communications auto-squelch system. The device 200 is full duplex in that it can communicate in both Rx (uplink) and Tx (downlink) directions. The alarm detection module function described in FIG. 1 is here performed with an Rx alarm detection circuit 202 to read incoming signals, and a programming and control block 204 to process the receive signals and determine if an alarm condition exists. Further, an Rx pattern generation block 206 generates the alarm-condition signal in response to commands（命令）from the programming block 204. An Rx MUX 208 passes the received signal or the alarm-condition signal in response to commands from the programming block 204. Duplicate functionality exists in the Tx link. Further, the Rx MUX 208 can be used to wrap-around（巻き込む？）a Tx link signal into the Rx link. For example, the wrap-around signal（巻き込み信号？）can be an alarm-condition signal generated by Tx pattern generation block 210. That is, the user can configure any alarm-condition signal to run from any device input, to any device output."
US9347851
"In certain embodiments of the invention, the selection of the frequency and velocity values for use is determined as follows. The mathematical modeling predicts specific values, but these values are verified by reviewing the data acquired. The process produces a verification signal that has traveled over 360° around the pipe. If the verification signal is the reflection from a long seam weld, it has traveled over 180° down and back. If the verification signal is the pitch catch wrap-around signal（回り込み信号；パイプを一周した信号）, it has traveled over 360° from one transducer to the other transducer. Since the pipe diameter is known and the transducer separation is known, the distance the wrap-around signal traveled is also known."
US20110019728
"As previously mentioned, the above-examples illustrated in FIGS. 12-18 are based on application of a superframe (i.e., a controlled sequence of frames) using a pulse shift and wrap around modification operation to suppress the carrier. However, other techniques can also be used to suppress the carrier and other techniques can be used to control the modulation sequencing. In a particular example, the modulation sequencing, using the superframe concepts described above, can be applied to a chopped PWM signal, a pulse shift with no wrap around signal（巻き込み信号？）, a PWM signal with a suppressed carrier based on other carrier modulation techniques, or any combination thereof, to achieve results similar to those illustrated in FIGS. 14-19."
"With wrap around（巻き込み、包含？）, when a PWM pulse that is wider than T/2 is shifted by −T/4, any portion of the pulse that would fall into the previous frame (i.e., that would cross the frame boundary) is placed at the end of the current frame (i.e., is wrapped around)."
US8816489
(Abstract)
"Methods for fabricating integrated circuit devices on an acceptor substrate devoid of （無い、有さない）circuitry are disclosed. Integrated circuit devices are formed by sequentially disposing（配設）one or more levels of semiconductor material on an acceptor substrate, and fabricating（作製）circuitry on each level of semiconductor material before disposition（配設）of a next-higher level. After encapsulation of the circuitry, the acceptor substrate is removed and semiconductor dice are singulated（単一化、個片化）. Integrated circuit devices formed by the methods are also disclosed."
"Conventionally（通常）, three-dimensional (3D) integrated circuit (IC) devices have been fabricated to improve chip density, by initially forming individual circuit devices and subsequently stacking（重ね、積層）and bonding（貼り合わせ）the chips together to form a multi-level chip stack or assembly. Consequently, the time, materials and process acts expended（要する）in carrying out individual chip fabrication, forming an assembly and electrically connecting the chips results in undesirably high cost. Moreover, stacking and electrical connection of the individually fabricated chips may lead to increased resistance and signal delay in the overall circuit due to undesirably long signal paths. Further, transmission of signals through wiring of one layer of the assembly may electrically interfere with（干渉）wiring on other layers, e.g., cross-talk.
Another technique that has been suggested to increase chip density, for minimization of design dimension（設計寸法）, is a so-called “bottom-up” approach. In this approach, circuits are fabricated conventionally on a base substrate, such as a silicon-on-insulator (SOI) wafer, followed by growth of successive layers of silicon on the wafer to provide an active surface and fabrication of additional circuit levels on each successive silicon layer prior to growth of the next-higher level. The process is repeated to create a device having a desired number of layers. One of the difficulties of this approach is that each circuit level, other than the last fabricated, is exposed to multiple thermal cycles as subsequent levels are formed. Further, due to the thermal cycling required by a bottom-up approach, suitable material choices for circuit structures are limited. Additionally, this approach requires an excessive amount of time as a consequence of growing each new layer of silicon on the base substrate.
Further, the foregoing（上記）approaches to multi-level circuit fabrication each require the use, and consumption, of a silicon wafer or other bulk substrate, which bulk substrate comprises（構成、成す、占める）a significant portion of the total cost of the fabrication process, on the order of twenty to thirty percent.
Accordingly, there are needs for processes to make 3D integrated circuits more efficiently and with reduced expense, while facilitating（容易化）minimization of the overall dimensions of the device."
"An embodiment of a process for fabricating a multi-level integrated circuit according to the present invention is described. In FIG. 1A, a sacrificial material 102 is formed on a base substrate（基板）, which may also be characterized as an acceptor substrate 100. A passivation material 104 is then formed on sacrificial material 102, followed by another, dielectric material 106. Acceptor substrate 100 may comprise（成る、構成される、含む）, by way of non-limiting example, monocrystalline silicon, and may comprise a new wafer or a reject wafer on which defective semiconductor devices have been fabricated. Acceptor substrate 100 may also comprise a substrate of another material, such as a ceramic, having a coefficient of thermal expansion (CTE) similar to that of a semiconductor material of a donor substrate to be bonded thereto as described below, to which sacrificial material 102 may bond, and highly resistant to an etchant for sacrificial material 102. In any case, acceptor substrate 100 may be of sufficient thickness and structural integrity to withstand mechanical stresses thereon without detectable deformation during handling and processing. Sacrificial material 102 may comprise a material which may be etched selective to silicon such as, by way of example, a silicon oxide (SiOx, e.g., SiO or SiO2), and may comprise（有する）a thickness of, for example, between about 2000 Å and 2 μm.
As shown in FIG. 1Band independent of the foregoing process described in association with FIG. 1A, a donor substrate 200 is processed. The donor substrate 200 may comprise any structure that includes a layer of semiconductor type material including, for example, silicon, germanium, gallium arsenide, indium phosphide, and other III-V or II-VI type semiconductor materials. By way of non-limiting example（非限定の例）, the donor substrate 200 may comprise silicon. The donor substrate 200 will be used to dispose a semiconductor foundation material over acceptor substrate 100, as described in further detail below.
As a non-limiting example, the foundation semiconductor material may be placed on acceptor substrate 100 by a process described herein using a modification of so-called SMART-CUT® technology.
However, other processes suitable for fabricating a semiconductor material on the surface of acceptor substrate 100 may also be used, if sufficiently low processes temperatures are maintained. In conventional implementation（実施態様）of SMART-CUT® technology, donor and acceptor wafers are bonded together using a high temperature anneal, on the order of about 1000° C. to about 1300° C. Such temperatures are unacceptable for use when a substrate already bears（有する）circuitry fabricated thereon. For example, processing temperatures should not exceed about 800° C. when flash memory（＊無冠詞）is fabricated. However, an additional plasma activation act may be integrated into（一体化）a conventional SMART-CUT® technology fabrication process to lower a required substrate bonding temperature, as described in detail below.
In an embodiment, a plurality of（複数の）ions of rare gases (e.g., neon, argon, krypton, or xenon), hydrogen, or helium may be implanted into the donor substrate 200 to form an implanted region 202. As represented by directional arrows（矢印で示す）204, a conventional ion source (not shown) may be used to implant the plurality of ions into the donor substrate 200 in a direction substantially perpendicular to a major surface（主表面）206 of the donor substrate 200 to create the implanted region 202, which may also be characterized as a transfer region, the inner boundary 208 of which is shown in the donor substrate 200 in broken lines（破線）. As known in the art, the depth to which the ions are implanted into the donor substrate 200 is at least partially a function of the energy with which the ions are implanted. Generally, ions implanted with less energy will be implanted at relatively lesser depths, while ions implanted with higher energy will be implanted at relatively greater depths. The inner boundary 208 of implanted region 202 lies（ある、位置する）substantially parallel to the major surface 206 of the donor substrate 200 and is at a preselected depth which is dependent on selected parameters of the atomic species implant process, as is well known to one of ordinary skill in the art. As a non-limiting example, hydrogen ions may be implanted into the donor substrate with an energy selected to form the inner boundary 208 at a depth D of between about eighty nanometers (80 nm) and about five hundred nanometers (500 nm) (about 800 Å to about 5000 Å), and more particularly, of about two hundred nanometers (200 nm) (about 2000 Å) within the donor substrate 200.
The inner boundary 208 of implanted region 202 comprises a layer of microbubbles or microcavities (not shown) comprising the implanted ion species, and provides a weakened structure within donor substrate 200（＊無冠詞）. The donor substrate 200 may then be thermally treated at a temperature above that at which ion implantation is effected（実施、行う）, in accordance with the disclosures of the patent documents in the preceding paragraph, to effect（引き起こす、生ぜしめる）crystalline rearrangement in the semiconductor material of the donor substrate 200 and coalescence of the microbubbles or microcavities.
An attachment surface 210 to be bonded to dielectric material 106 on acceptor substrate 100 (FIG. 1A) may be formed on donor substrate 200 by exposing the major surface 206 of the donor substrate 200 to a reactive ion etching (RIE) plasma including hydrogen or an inert gas (e.g., argon, oxygen, or nitrogen) to form a plasma-activated major surface 206′. The plasma-activated major surface 206′ increases the kinetics（動特性、速度）of a subsequent bonding act in the form of an oxide reaction with an adjacent surface of the dielectric material 106 overlying the acceptor substrate 100 due to the increased mobility and reactivity of the ionic species (e.g., hydrogen) created on attachment surface 210. By utilizing a plasma-activated material, the wafer bonding process may be performed at temperatures of less than about four hundred degrees Celsius (400° C.). Plasma-activated bonding is described in U.S. Pat. No. 6,180,496 to Farrens et al., assigned to Silicon Genesis Corporation.
As shown in FIG. 1C, the donor substrate 200 is disposed on the dielectric material 106 carried by acceptor substrate 100 and may be bonded to the dielectric material 106 using an annealing process. The plasma-activated major surface 206′ enables annealing at a substantially reduced temperature, as noted above, in comparison to those employed in conventional wafer bonding techniques. Further, the hydrogen or other ions implanted in ion implanted region 202 to the depth of inner boundary 208 makes the silicon in the thermally treated donor substrate 200 susceptible to （易く、しやすく）breakage substantially along inner boundary 208 when a shear force is applied substantially parallel to the major plane（主平面）of the donor substrate 200. After attaching the donor substrate 200 to the dielectric material 106 on acceptor substrate 100, the portion of the donor substrate 200 on the side of（側）the inner boundary 208 opposing（対向、対面）the dielectric material 106 may be cleaved or fractured by applying a shearing force to the donor substrate 200. The portion of the donor substrate 200 below the inner boundary 208, of a thickness, for example, of between about eighty nanometers (80 nm) (about 800 Å) and about four hundred nanometers (400 nm) (about 4000 Å), for example, about two hundred nanometers (200 nm) (about 2000 Å), is detached from the remainder of donor substrate 200 and remains bonded to the acceptor substrate 100 through dielectric material 106, passivation material 104 and sacrificial material 102 to form a foundation material 212, as shown inFIG. 1D.
US8765578
"A method of edge protecting bonded（貼り合わせ）semiconductor wafers.（＊体言止め）A second semiconductor wafer and a first semiconductor wafer are attached（貼付け、取付）by a bonding layer/interface and the second semiconductor wafer undergoes（受ける、経る、される）a thinning process（薄膜化？）. As a part of the thinning process, a first protective layer is applied to（付ける、塗布？）the edges of the second and first semiconductor wafers. A third semiconductor wafer is attached to the second semiconductor wafer by a bonding layer/interface and the third semiconductor wafer undergoes a thinning process. As a part of the thinning process, a second protective layer is applied to the edges of the third semiconductor wafer and over the first protective layer. The first, second and third semiconductor wafers form a wafer stack. The wafer stack is diced into a plurality of 3D chips while maintaining the first and second protective layers."
ウェーハー貼り合わせ: wafer bonding；ASCIIデジタル「半導体プロセスまるわかり」
Silion on insulator; Wikipedia
"Wafer bonding[14][15] – the insulating layer is formed by directly bonding oxidized silicon with a second substrate. The majority of the second substrate is subsequently removed, the remnants（残り）forming the topmost Si layer.
One prominent（よく知られた、代表的）example of a wafer bonding process is the Smart Cut method developed by the French firm Soitec which uses ion implantation followed by controlled exfoliation to determine the thickness of the uppermost silicon layer."
ソニーバイオ、windows10ですが、多分10に更新後画面の輝度調節ができなくなりました。コントロールパネルや設定や、ＫＢからのＦキーでの調節もできない。カスタマに電話で聞いても不明。
ネットで調べて、デスクトップ画面にして右クリックでインテルグラフィックスパネルを出せば、輝度やコントラストの調節ができると分かりました。しかし設定が微妙で、変な色調になったりして、どうも何かが違うような気がします。
US8400548
"1. A computer-implemented（コンピュータ実施、実行）method for generating and synchronizing interactive Augmented Reality (AR) displays（ディスプレイ、表示）, comprising: capturing（撮影）live video（ビデオ；＊無冠詞）of a real-world, physical environment and displaying the live video on a touch sensitive surface of a device; combining an information layer and the live video, the information layer related to（過去分詞；＊being無し）one or more objects in the live video; modeling computer-generated imagery based on the live video; displaying the computer-generated imagery representing one or more objects in the live video on the touch sensitive surface; overlaying（重ねる、重畳）the information layer on the computer-generated imagery; receiving sensor data from one or more onboard motion sensors indicating that the device is in motion; and synchronizing the display of the live video, the computer-generated imagery and the information layer on the touch sensitive surface using the sensor data."
"BACKGROUND
Augmented Reality (AR) technology combines a live view of a real-world, physical environment with computer-generated imagery. Information about the real world environment can be stored and retrieved as an information layer which can be overlaid on the live view and interacted with（相互作用）by a user. Despite strong academic and commercial interest in AR systems, many existing AR systems are complex and expensive making such systems unsuitable for general use by the average consumer."
"FIG. 1A illustrates an exemplary（例）device for receiving live video of a real-world, physical environment."
"FIG. 1A illustrates example device 100（＊無冠詞）for receiving live video of a real-world, physical environment. Device 100 can be any device capable of supporting AR displays, including but not limited to（含むが限定しない）personal computers, mobile phones, electronic tablets, game consoles, media players, etc. In some implementations, device 100 can be an electronic tablet having a touch sensitive surface 102. In one embodiment, device 100 can include a video camera on a back surface (not shown). Other device configurations are possible including devices having video cameras on one or more surfaces.
In the example shown, the user（＊初出だが定冠詞；図示無し）is holding device 100 over a circuit board. A live video 104 of the circuit board is shown on surface 102. Various objects are shown in live video 104. For example, the circuit board shown includes processor chip 106, capacitor 108, memory cards 110 and other components. The circuit board also includes bar code 112 and markers 114a, 114b. Virtual button 115 can be used to capture one or more frames of live video."
US8905855
(Abstract)
"System and method（＊無冠詞）for utilizing motion capture data for healthcare compliance, sporting, gaming, military, virtual reality, industrial, retail loss tracking, security, baby and elderly monitoring（見守り）and other applications for example obtained from a motion capture element and relayed to a database via a mobile phone. System obtains data from motion capture elements, analyzes data and stores data in database（＊無冠詞）for use in these applications and/or data mining, which may be charged for（有料）. Enables（＊主語省略）unique displays associated with the user, such as 3D overlays（重ね、重畳）onto images of the user to visually depict the captured motion data. Ratings, compliance, ball flight path data can be calculated and displayed, for example on a map or timeline or both. Enables performance related equipment fitting and purchase. Includes active and passive identifier capabilities."
"1. Field of the Invention
One or more embodiments setting forth（記載、説明）the ideas described throughout this disclosure pertain to the field of motion capture data and displaying information based on motion analysis data associated with a user or piece of equipment based on previous motion analysis data from the user or other user(s) and/or piece of equipment. More particularly, but not by way of limitation, one or more aspects of the disclosure enable a system and method for utilizing motion capture data that enables use of（＊文法的におかしい気がする。enableに対応するto useとなるべきだと思う）actual motion capture data obtained from portable wireless motion capture elements such as visual markers and sensors, radio frequency identification tags and mobile device computer systems for healthcare compliance, sporting, gaming, military, virtual reality, industrial, retail loss tracking, security, baby and elderly monitoring and other applications."
US20030022921
"U.S. Pat. No. 4,822,807 further describes（記載）that when torsemide modification II is present in very finely divided form in pharmaceutical tablets, it rearranges into torsemide modification I, with the result that（結果）the rate of dissolution of the active material upon（時、すると）introducing the tablets into water can be significantly changed. The dissolution rate is an important characteristics of a pharmaceutical dosage form and, in order to dose（服用、投薬）reproducibly（再現性良く）, must not differ from one tablet to the next.
[0008] There remains a need in the art for（必要、需要、求め）pharmaceutical formulations containing torsemide modification II, wherein the torsemide modification II does not rearrange into torsemide modification I and remains stable with regard to dissolution rate.
US7429115
(Abstract)
"A mirror system for a vehicle having driver's side viewing device located in a mirror housing mounted on（取付、配設、設ける、搭載）the vehicle wherein a first section of the mirror housing contains a viewing surface in the interior of the vehicle and a second portion of the mirror housing is optically open to the outside（外部）of the vehicle; said first section of the mirror housing adapted to（構成、適合）contain one or more substantially right angle triangular prisms having two sides of substantially equal length and two vertices of substantially equal angles; said prism mounted in the first section of the mirror housing so that one of the two sides of equal length of said prism is positioned in an opening facing（臨む、面する）the interior of the vehicle to provide a viewing surface; the second one of the sides of equal length is facing to（臨む、面する）the exterior of the vehicle; said second section of the mirror housing sized（大きさ、寸法）and shaped to contain operative optical elements comprising one or more reflective means mounted in the second section of the mirror housing at an angle to the second one of the sides of equal length of the prism(s) in the first section of the mirror housing so that when the driver looks through the viewing surface of the prism he can see objects to the side（側面）and rear of the vehicle."
US5718759
(Abstract)
"A cementitious（セメント質）composition useful for water-resistant construction materials, including floor underlayments（下敷き、下張り）, backing boards, self-leveling（セルフレベリング）floor materials, road patching materials, fiberboard, fire-proofing sprays, and fire-stopping（防火）materials includes about 20 wt. %（重量パーセント）to about 75 wt. % calcium sulfate beta-hemihydrate, about 10 wt. % to about 50 wt. % Portland cement, about 4 wt. % to about 20 wt. % silica fume and about 1 wt. % to about 50 wt. % pozzolanic aggregate. The Portland cement component may also be a blend（混合物）of Portland cement with fly ash and/or ground blast slag."
"The invention relates to cementitious compositions and in particular to cementitious construction materials such as floor underlayments, backer boards, floor and road patching materials, fiberboard, fire-proofing sprays, and fire-stopping materials made from（＊"such as"を代表している"cementitious construction materials"に係ると思う）a composition comprising（から成る）gypsum, Portland cement and silica fume."
"Construction materials, such as backer boards for showers and floor underlayments, typically do not contain gypsum because gypsum（石膏）-containing materials are usually not water resistant. However, gypsum is a desirable component in construction materials due to its rapid cure（硬化）and early strength characteristics. Attempts to improve the water-resistance of gypsum boards by mixing Portland cement and gypsum (calcium sulfate hemihydrate) have met with limited success（限られた、わずかな、不十分な成功）because such a mixture can result in the formation of ettringite, which may cause expansion of the gypsum/Portland cement product and thus lead to its deterioration（劣化、悪化）. Ettringites are formed when tricalcium aluminate (3CaO.multidot.Al.sub.2 O.sub.3) in the Portland cement reacts with sulfate."
Self-leveling concrete, Wikipedia
"In the category of self-leveling concrete there are two main groups of materials: underlayments and toppings. Underlayments are installed over an existing subfloor to smooth it out and correct any surface irregularities（凹凸）prior to the installation of all types of floor coverings, including sheet vinyl, vinyl composition tile (VCT), wood, ceramic tile and carpet."
US4569831
(Abstract)
"An apparatus and process（＊無冠詞）for calcining（焼成）gypsum is disclosed which utilizes（＊主語単数扱い）a flash furnace for rapidly calcining fine particulate gypsum while the material is suspended in a stream of hot gas. The method and apparatus utilize（＊主語複数扱い）a two-stage suspension preheater for utilizing waste gases from the calcining furnace for preheating raw material to be calcined（焼成対象）and a two-stage suspension cooler for cooling hot calcined gypsum which is discharged from the calcining furnace. Spent cooling gas is supplied to the preheater for use in preheating the fresh gypsum to be calcined. The invention also contemplates（検討、考慮）recirculating a portion of the gypsum discharged from the furnace back to the furnace for further calcination. Hot product may be discharged directly from the furnace."
US5927968
(Abstract)
"A method and apparatus is（＊主語単数扱い）disclosed for the continuous calcining of gypsum material in a high-efficiency, refractoryless kettle preferably（好適）heated by a multiple series of separate immersion tube burner coils, each coil operating within a specific calcining zone inside the kettle. The lowest, i.e., initial, burner tube coil is formed with（形成されている）a low profile to permit use of a small initial gypsum charge, and hence, a quick kettle start-up cycle. That low profile initial burner design also helps keep the agitator motor's load at a minimum during cycle start-up. Due to the immersion tube burner coil construction, no refractory structure for the kettle is required. Also, no separate hot pit structure is required, as the kettle is used to merely hold the material being calcined and no residual heat is present. A relatively thin kettle can be constructed（構成、作製）, as it need only withstand relatively low operating temperatures. The kettle's staged, interiorly-disposed（内設）burner tube coils act（作用）to directly transfer burner tube heat to the kettle's contents, and the coils exhaust（排熱？）exteriorly of the kettle. The present calcining method and apparatus permits substantially improved tonnage output of calcined material, for a kettle of a given size. A modification to the present apparatus includes structure for recovering and recycling a portion of the spent burner gases, and also separate structure for forced aeration air, both preferably for introduction through the kettle bottom."
US4415543
"The dust from the calcining furnace（焼成炉；kilnとの違いは？）and, if desired, the dried sludge from the phosphoric acid may also be added to the molten product in the electric furnace and thus incorporated into the final calcium silicate co-product(s)."
