積層

US7511939
(Abstract)
"A layered（積層）capacitor structure comprises two or more semiconductor/dielectric plates formed above an insulating surface which provides mechanical support, with the plates arranged（配設、配置）in a vertical stack（積層体）on the insulating surface. An insulating layer is on each plate, patterned and etched to provide an opening which allows the top of one plate to be in physical and electrical contact with the bottom of the subsequent plate. Contact openings are provided through the insulating layers, each of which provides access to a respective（それぞれ、各々）semiconductor layer and is insulated from any other（その他）semiconductor/dielectric plate. Electrical contacts through the contact openings provide（得られる、もたらす、可能とする）electrical connections to respective semiconductor layers. The present structure can include as many stacked layers（層の積み重ね）as needed to provide a desired total capacitance or range of capacitances."

"1. Field of the Invention

This invention relates generally to integrated circuit (IC) capacitors, and more particularly to a layered capacitor architecture and fabrication method.

2. Description of the Related Art

Integrated circuits（＊無冠詞複数、一般）frequently require the use of one or more capacitive devices, which serve numerous purposes in both analog and digital circuits. For example, a capacitor（＊不定冠詞、具体例）can provide an integration function, serve as part of a filter design, act as an energy or data storage device, or provide a bypass or decoupling capacitance on an IC.

However, a capacitor integrated on an IC die is necessarily（必然的）small, and thus inherently（元来、本質的、避けられない）limited with respect to the amount of capacitance it can provide. At the same time, modern electronic circuits require devices with ever greater（より大きな）capacitances. However, as integration density（＊無冠詞）increases, chip space（＊無冠詞）for large capacitors is less readily available. Numerous capacitor designs are known for providing increased capacitance by increasing the area of their conductive plates, and/or reducing the thickness of their dielectric layer. However, these devices remain limited（依然として、未だに、まだ限定）in their ability to provide high capacitance values, due to the limited chip area typically allotted for capacitors.

Off-chip devices can provide large capacitances, but often cannot be used due to their size, as well as the length and number of connections required and the attendant signal propagation times, resistive voltage drops and connection inductances.

SUMMARY OF THE INVENTION

A layered capacitor architecture and fabrication method are presented（提供）which enables a designer to provide a relatively high capacitance in a limited amount of chip area.

The structure of the present integrated circuit capacitor structure is fabricated（作製）on an insulating surface which provides mechanical support. Two or more semiconductor/dielectric plates are arranged in a vertical stack on top of the insulating surface, each of which comprises a first semiconductor layer and a dielectric layer on the semiconductor layer, the semiconductor and dielectric layers patterned and etched such that they have a desired pattern, and such that（＊such thatの繰り返し）each pair of semiconductor layers separated by a dielectric layer form a capacitor. The structure also includes a topmost（最上位）layer which forms a capacitor with the topmost semiconductor/dielectric plate.

An insulating layer is deposited on each semiconductor/dielectric plate, and is patterned and etched to provide an opening such that the semiconductor layer of the plate immediately above the insulating layer is in physical and electrical contact with the dielectric layer of the plate immediately below the insulating layer.

After all plates have been formed, contact openings are made（設ける）through the insulating layers, each of which provides access to a respective semiconductor layer. The structure is arranged such that each contact opening provides access to one semiconductor layer, and is insulated from all other semiconductor/dielectric plates. Electrical contacts are provided through the contact openings and to the topmost layer to provide electrical connections to respective semiconductor layers.

Stacking（重ねる、積層）two capacitors in this way essentially reduces the required die area by 50% in comparison with a comparably-sized（同等）conventional capacitor. The present structure can include as many stacked layers as needed to provide a desired total capacitance or range of capacitances. In this way, total area consumed by a capacitor on a given integrated circuit is reduced in comparison with a comparably-sized conventional capacitor.

These and other features, aspects, and advantages of the present invention will become better understood with reference to the following drawings, description, and claims.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1is schematic diagram illustrating the layered capacitor architecture of the present invention.

FIGS. 2a and 2 b（＊図番の英字が小文字）are sectional and corresponding plan views of a layered capacitor per the present invention.

FIGS. 3a-14 a are sectional views illustrating a method of fabricating a layered capacitor per（従う）the present invention."

US7857886
"The present invention relates to laminated ceramic capacitors（積層セラミックコンデンサ）also known as multi layered ceramic chip capacitors (MLCC)（積層セラミックコンデンサ；村田製作所）, and particularly to the internal electrode material used in the fabrication of such capacitors.

 

Multi layered ceramic chip capacitors generally consist of（から成る）a dielectric ceramic matrix with embedded metal sheet electrodes of some μm（数ミクロン）thickness and some 10 μm of distance. In manufacturing such capacitors, suitable pastes of powdered ceramic matrix precursor material and suitable pastes of a metal powder are alternatively laminated（積層）on each other. Sometimes there is also provided a thin intermediate material. After lamination（積層）the laminate（積層体）is dried and heated to about 300 to 450° C. (normally under air（空気下（空気中？）) to decompose the organic binder of the pastes. Thereafter the laminate is further heated under vacuum or inert gas atmosphere（雰囲気下で）to about 1000 to 1350° C., mostly to at least 1200° C., for sintering（焼結）and formation of the ceramic dielectric material."