library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity cpld_state_test is
port (
clk : in std_logic;
add_out : out std_logic_vector(7 downto 0);
start_sign : in std_logic;
reset_sign : in std_logic;
we_signal : out std_logic;
oe_signal : out std_logic;
end_signal : out std_logic);
end cpld_state_test;
architecture rtl of cpld_state_test is
signal status : std_logic_vector(2 downto 0):= (others=>'0');
signal address : std_logic_vector(7 downto 0):= (others=>'0');
begin
process (clk)
begin
if (clk'event and clk='1') then
case status is
when "000" => -- reset mode
address <= "00000000";
status <= "001";
we_signal <= '1';
oe_signal <= '1';
when "001" => -- waiting start signal
end_signal <= '0';
if ( start_sign = '1' ) then
status <= "010";
end if;
when "010" => -- write enable (start loop)
we_signal <= '0';
status <= "011";
when "011" => -- write disable
we_signal <= '1';
status <= "100";
when "100" => -- count up address
address <= address + 1;
status <= "101";
when "101" => -- check to reach 32kB
if ( address = "11111111" ) then
status <= "110"; -- goto end
else
status <= "010"; -- goto loop
end if;
when "110" => -- output end_signal when reached 32kB
end_signal <= '1';
status <= "000";
when others => null;
end case;
end if;
end process;