裏面基準

WO2013180447; JP
"When flatness of the epitaxial wafer on which the back surface depositions have been produced is measured on the basis of the position of the back surface（裏面基準で）, the thickness of the epitaxial wafer precipitously increases at the outer peripheral portion, which results in flatness deterioration."

WO2014065949
"It is noted that US8436366 does not use the same measurement protocol to measure TTV, the figures in US8436366 show a back side referenced（裏面基準の）, or chucked, measurement while the TTV measurements reported in this work are based on a floating substrate. As a result the comparison of TTV values between this invention and US8436366 is not direct."

うねり

WO2016070036
"With the promising beaker test results, the new Si etchant was tested using an SSEC single-wafer processor on regular test wafers and ground wafers. The ground wafers were thinned（薄くされた）by Strasbaugh using the same grinding parameters as for real TSV device wafers. Therefore, the surface roughness, waviness（うねり）, texture, and thickness variations are the same as they would be for TSV wafers. Table 2 summarizes the etch data generated in the SSEC single-wafer tool."

WO9918612
"A wafer is typically a disc, typically 4, 6, 8, or 12 inches in diameter and typically having a thickness between 400 microns and 6 mm. The substrate wafer may be of any desired configuration. The substrates are preferably optically transparent and flat, i.e., have less than some variation in surface height across the surface thereof, e.g., less than one wave（うねりが１つもない）, depending on the requirements of the desired application." 

US2015303049(JP)
"5. The method for processing a semiconductor wafer according to claim 1, wherein when frequency analysis is performed on a surface height of the wafer following the double-side planarizing step, an amplitude of a wave（うねりの振幅）in a wavelength region of 100 mm or less is in the range of 1.0 μm or less."

WO2017068165
" It has been found that known manipulators may not optimally suitable for the correction of all image errors. Overlay errors for example involve correction concepts that cannot be realized in an optimum way via the manipulators known from the prior art. With concepts known so far, it is generally possible with difficulty to realize high degrees of waviness（うねり）on optical elements, which may be involved in particular for the correction of overlay errors. The waviness is in this case a measure（尺度）of how many wave peaks or wave troughs（波谷）occur in a cross-sectional representation of the optical element over the entire lateral extent of the optical element."

WO0143184
"A flat smooth substrate surface 30, free of（無い）irregularities（凸凹）, corrugations（しわ）, asperities（ざらざら）, waves（うねり）or undulations（起伏）, is preferred. Such a surface can be prepared by machining, for example, by grinding, polishing or smoothing the sintered substrate, as is known in the art."

影響を与える

WO2014105044
"While this grinding process can improve flatness and/or parallelism（平行度）of the ground wafer surfaces, subsequent processes can impact（影響を与える）the wafer and cause topology degradation. For example, as a result of lattice mismatch between a heavily doped substrate and a lightly doped epitaxial layer, a bow（湾曲）and a warp（反り）of the wafer changes substantially after[＊alter] the epitaxial layer deposition."

WO2016106196
"17. A three-dimensional optical image acquisition system comprising:
a plurality of cameras each configured to view a measurement space from a different point of view;
at least one projector configured to project a pattern onto the measurement space;
a controller configured to perform a full calibration of the plurality of cameras and the at least one projector to generate at least a first set of correction values and a second set of correction values; and
wherein the controller is configured to perform a calibration update relative to each
camera/projector pair, wherein the calibration update affects（影響を与える）the first set of correction values while leaving the second set of correction values unchanged."

WO2014100581
"35. A method of decreasing the salinity of water comprising
(a) providing a flow of saltwater through the inlet channel of the device defined by any one of claims 1-30 or the water inlet of the system defined by any of claims 31-34;
(b) applying a potential bias to generate an electric field gradient that influences（影響を与える）the flow of ions through the desalination unit of the device defined by any one of claims 1- 30 or the desalination units of the system defined by any of claims 31-34; and
(c) collecting water from the dilute outlet channel of the device defined by any one of claims 1-30 or the water outlet of the system defined by any of claims 31-34;
wherein the water collected from the dilute outlet channel of the device defined by any one of claims 1-30 or the water outlet of the system defined by any of claims 31-34 has a lower electrical conductivity than the saltwater."

WO2010085647
(Ab)
"Memory devices and methods are described that include a stack of memory dies and a logic die. Method and devices described include those that provide for repartitioning the stack of memory dies and storing the new partitions in a memory map. Repartitioning in selected configurations allows portions of memory to be removed from use without affecting（影響を与えることなく）the rest of the memory device. Additional devices, systems, and methods are disclosed."

WO2013169356
"35. A wireless remote temperature sensor comprising:
a resonant circuit having a receiver coil and a capacitance, said receiver coil configured to receive power from an inductive transmitter; and
a substrate selected to vary in size in response to a change in temperature, said receiver coil supported by said substrate such that said substrate causes variation in a size or shape of said receiver coil when said substrate undergoes said change in temperature, said variation being sufficient to materially affect（大きな影響を与える）a reflected impedance of said receiver coil in the inductive transmitter."

WO2013148664
(Ab)
"An apparatus for forming a glass sheet with reduced thermal coupling between upper and lower regions of the apparatus is disclosed. The apparatus allows for temperature changes near the lower regions of the enclosure without a large temperature impact（温度に大きな影響を与えず）on the upper regions of the enclosure, thereby providing for greater flexibility in setting a temperature profile for a forming body located within the enclosure."

WO2011002688
(Ab)
"A method is disclosed for adjusting the composition of plasmas used in plasma doping, plasma deposition and plasma etching techniques. The disclosed method enables the plasma composition to be controlled by modifying the energy distribution of the electrons present in the plasma. Energetic electrons are produced in the plasma by accelerating electrons in the plasma using very fast voltage pulses. The pulses are long enough to influence（影響する）the electrons, but too fast to affect the ions significantly（大きな影響を与える）. Collisions between the energetic electrons and the constituents of the plasma result in changes in the plasma composition. The plasma composition can then be optimized to meet the requirements of the specific process being used. This can entail changing the ratio of ion species in the plasma, changing the ratio of ionization to dissociation, or changing the excited state population of the plasma."

研削時

WO2016089675
"The inventors discovered（発見）that when the shaped abrasive particles are rotated a significant angular amount relative to the longitudinal axis of the belt, due to the aggressive cut of the shaped abrasive particles, the belt may have a tendency to track off to the side（側方へと軌道を外れる）of the grinding machine; especially, as the load on the work piece is significantly increased. This can be especially problematic in situations when（状況において）a high work piece load is applied for a short duration, the work piece removed from the belt, and then reapplied for another short duration high load cycle. The belt tracking system of the grinding machine sees（＊～システムにおいて～が起こる）repeated cycles with high belt side load and then no belt side load. Adjusting the belt to track properly with no side load present can cause the belt to not（＊to不定詞、cf. "not to"）track properly when the side load is present and vice versa. This problem is most acute for（において顕著）abrasive belts that are short, narrow, or under low tension and contain larger sized shaped abrasive particles. The inventors determined that one way to solve this problem was to limit the angular rotation of the shaped abrasive particles on the belt thereby limiting the generated side loads during grinding（研削時に）while still providing a non-scribing, finer finish on the work piece." 

WO2011156228
"The via holes are fabricated at this time using TSV processes. The dicing tape is removed from the back side of the wafer and another support tape is applied to the top side of the wafer to protect the circuitry during back side grinding（裏面側研削時に）."

多層化

WO02073699
"19. The multilayer nanostructure of claim 1, wherein at least some nanowires are multilayered（多層化）."

WO2016081272
"[0045] In contrast to the above described multi-lamination（多層化）process, Figure 7 illustrates a subpad fabrication process involving coating of pressure sensitive adhesive layers onto the subpad material, in accordance with an embodiment of the present invention."

給電電極

WO2015074917
(Ab)
"Light sources (1) such as retrofit light emitting diode tubes comprise light circuits (11) with light emitting diodes (12) and feeding electrodes（給電電極）(13, 14), terminals (21-24) for exchanging signals with ballasts (2, 3) or supplies (4, 5), and filament circuits (31, 41) for coupling the terminals (21-24) and the feeding electrodes (13, 14)"

WO2016048944
"The gas or gases to form the plasma are injected radially inward through the reactor wall to an exit pumping port in the center of the chamber. Substrate 14 is positioned proximate RF-powered electrode（ＲＦ給電電極）16. Electrode 16 is insulated from chamber 12 by a polytetrafluoroethylene support 18."

"The substrate is located on the powered electrode（給電電極）in the chamber, and the chamber is evacuated to the extent necessary to remove air and any impurities."

WO2011115945
"In this case, the remote controlled switch 156 can disconnect the "grounded" leg 155 from the extraction power supply 121 and electrically connect it to the other leg 154. In this fashion, the antenna 152 is acting as a powered electrode（給電電極）and the chamber walls are acting as a ground electrode."

WO2012176045
" The concept of an AC current for tandem electrodes is well known in the art. U.S. Pat. No. 6,207,929 discloses a system whereby tandem electrodes are each powered by a separate inverter type power supply. The frequency is varied to reduce the interference between alternating current in the adjacent tandem electrodes. Indeed, this prior patent of assignee relates to single power sources for driving either a DC powered electrode（直流給電電極）followed by an AC elec-trode or two or more AC driven electrodes."

WO2011044343
"FIG. 38B is a cross-sectional view of a jaw of an alternative embodiment of an end effector illustrating steam control paths in supply electrodes（給電電極）, return electrodes, insulators positioned intermediate（中間に配置）the supply electrodes and the return electrodes, and a cutting member movable within the end effector."

WO2010107980
"Feed electrodes（給電電極）can be placed in direct contact with the skin in relatively close proximity（密接に）to generate a differential voltage which in turn generates alternating currents. The current flows primarily between the feed electrodes, while secondary currents flow into the human body to generate a differential voltage across the receiver electrodes."

WO2009006062
"Generally, an appropriate set of gases is flowed through an inlet in an upper electrode 202. The gases are subsequently ionized to form plasma 204 in order to process (e.g., etch or deposit) exposed areas of substrate 206, such as a semiconductor substrate or a glass pane, positioned with a hot edge ring (HER) 212 (e.g., Si, etc.) on an electrostatic chuck (ESC) 208, which also serves as a powered electrode（給電電極）."

半導体ウェーハの割れ

WO2012057893
"Integrated circuits, power semiconductors, light-emitting diodes, photonic circuits, microelectromechanical systems（マイクロマシン技術）(MEMS), embedded passive arrays, packaging interposers, and a host of（多くの）other silicon- and compound semiconductor-based（ベースとした）microdevices are produced collectively in arrays on wafer substrates ranging from（の範囲の）1 -12 inches in diameter. The devices are then separated into individual devices or dies that are packaged to allow practical interfacing with the macroscopic environment, for example, by interconnection with（と配線）a printed wiring board . It has become increasingly popular to construct the device package on or around the die while it is still part of the wafer array. This practice, which is referred to as wafer-level packaging, reduces overall packaging costs and allows a higher interconnection density（配線密度）to be achieved between the device and its microelectronic environment than with（に比べ）more traditional packages that usually have outside dimensions several times larger than the actual device. 

Until recently, interconnection schemes have generally been confined to two dimensions, meaning（つまり；＊すなわち）the electrical connections between the device and the corresponding board or packaging surface to which it is mounted have all been placed in a horizontal, or x-y, plane. The microelectronics industry has now recognized that significant increases in device interconnection density and corresponding reductions in signal delay (as a result of shortening the distance between electrical connection points) can be achieved by stacking（スタックする）and interconnecting devices vertically, that is, in the z-direction. Two common requirements for device stacking are: ( 1 ) thinning（薄くする）of the device in the through- wafer direction（ウェーハー貫通方向）from the backside（背面側）; and (2) subsequently forming through-wafer electrical connections（ウェーハー貫通の電気接続）, commonly referred to as through-silicon-vias or "TSVs," that terminate on the backside of the device. For that matter（ついでに言うなら；＊また）, semiconductor device thinning has now become a standard practice（標準的技法）even when devices are not packaged in a stacked configuration because（するため；＊理由）it facilitates heat dissipation（放熱）and allows a much smaller form factor to be achieved with compact electronic products such as cellular telephones. 

There is growing interest in（関心が高まっている）thinning semiconductor devices to less than 100 microns to reduce their profiles, especially when they or the corresponding packages in which they reside（属する）are stacked, and to simplify the formation of backside electrical connections on the devices. Silicon wafers used in high-volume integrated circuit production are typically 200 or 300 mm in diameter and have a through-wafer thickness of about 750 microns. Without thinning（薄層化）, it would be nearly impossible to form backside electrical contacts that connect with front-side circuitry by passing the connections through the wafer. Highly efficient thinning processes for semiconductor-grade silicon and compound semiconductors based on mechanical grinding（研削）(back-grinding) and polishing（研磨）as well as chemical etching are now in commercial use. These processes allow device wafer thickness to be reduced to less than 100 microns in a few minutes while maintaining precise control over（精密に制御しながら）cross- wafer thickness uniformity（厚みの横断的な均一性）. 

Device wafers that have been thinned to less than 100 microns, and especially those thinned to less than 60 microns, are extremely fragile and must be supported over their full dimensions（全面積に亘って）to prevent cracking（割れ）and breakage（破損）. Various wafer wands and chucks have been developed for transferring（移動）ultra-thin device wafers, but the problem still exists of（という問題がまだ存在）how to support the wafers during back-grinding and TSV-formation processes that include steps such as chemical-mechanical polishing (CMP), lithography, etching, deposition, annealing, and cleaning, because these steps impose（強いる；＊与える）high thermal and mechanical stresses on the device wafer as it is being thinned or after thinning. An increasingly popular approach to ultra-thin wafer handling involves（伴う）mounting（装着）the full-thickness device wafer face down to a rigid carrier with a polymeric adhesive. It is then thinned and processed from the backside. The fully processed, ultra-thin wafer is then removed（取り外し）, or debonded（剥離）, from the carrier by thermal, thermomechanical, or chemical processes after the backside processing has been completed." 

薄層化

WO2014058601
"14. The method of claim 1 , wherein processing the semiconductor wafer while it is bonded（接合）to the transparent handler includes thinning（薄層化）the semiconductor wafer."

"The present disclosure relates to wafer debonding（剥脱）and, more specifically, to advanced methods for handler wafer debonding. 

DISCUSSION OF THE RELATED ART 

Three-dimensional（三次元）(3D) chip technologies include 3D integrated circuits (IC) and 3D packaging. 3D chip technologies are gaining widespread importance（広範囲にわたって重要性を増しつつある）as they allow for（できるため；＊ので、理由）greater integration of more complex circuitry with shorter circuit paths allowing for faster performance and reduced energy consumption. In 3D ICs, multiple thin silicon wafer layers are stacked（積み重ね）and interconnected vertically to create a single integrated circuit of the entire stack（スタック）. In 3D packaging, multiple discrete ICs are stacked, interconnected, and packaged together. 

Modern techniques（現代の技法）for 3D chip technologies, including both 3D ICs and 3D packaging, may utilize through-silicon vias（シリコン貫通バイア）(TSV). A TSV is a vertical interconnect access (VIA) in which a connection passes entirely through a silicon wafer or die. By using TSVs, 3D ICs and 3D packaged ICs may be more tightly（ぎっしりと；＊高密度）integrated as（ため；＊ので、理由）edge wiring and interposer layers are not required. 

Temporary wafer bonding/debonding is an important technology for implementing （実施）TSVs and 3D silicon structures in general. Bonding（接合）is the act of attaching（取り付け）a silicon device wafer, which is to become a layer in a 3D stack, to a substrate or handling wafer so that it can be processed, for example, with wiring, pads, and joining metallurgy, while allowing the wafer to be thinned（薄層化）, for example, to expose the TSV metal of blind vias etched from the top surface. 

Debonding is the act of removing the processed silicon device wafer from the substrate or handling wafer so that the processed silicon device wafer may be added to a 3D stack. 

Many existing approaches（手法）for temporary wafer bonding/debonding involve the use of（使用を含む）an adhesive layer placed directly between the silicon device wafer and the handling wafer. When the processing（処理）of the silicon device wafer is complete, the silicon device wafer may be released from the handling wafer by various techniques such as by exposing the wafer pair to chemical solvents delivered by perforations in the handler, by mechanical peeling from（機械的に剥がす）an edge initiation point or by heating the adhesive so that it may loosen to the point where the silicon device wafer may be removed by sheering. 

3M has developed an approach which relies on light-to-heat-conversion (LTHC) whereby bonding is performed using an adhesive layer and a LTHC layer. Debonding is then performed by using an infrared laser to heat up the LTHC layer and thereby loosening or "detackifying（減粘性化する）" the adhesive to the point where the silicon device wafer may be removed. However, the LTHC layer is dark colored and highly opaque making it difficult to（＊分詞、結果）inspect the underlying circuitry prior to removing the silicon device wafer from the handling wafer, which is generally transparent. Moreover, the LTHC approach employs a YAG laser operating at the infrared (IR) wavelength of 1064nm, which while effective at generating heat in the LTHC layer and greatly diminishing the bonding strength of the adhesive, is not sufficient to fully and completely ablate the interface resulting in effectively zero adhesion." 

WO2008157001
"1. A method of manufacturing stacked（積層された）semiconductor assemblies, comprising: mounting（マウントする；＊取り付け）a semiconductor wafer to a temporary carrier wherein the wafer has a plurality of first dies arranged in a die pattern on the wafer; thinning（薄層化）the wafer; attaching（接着；＊取り付け）a plurality of singulated（単一化された）second dies to corresponding first dies, wherein the second dies are arranged in the die pattern and spaced apart from each other by gaps（間隙によって）; disposing（配置）an encapsulating material（カプセル化材料）in the gaps between the second dies; and thinning the second dies after attaching the second dies to the first dies."

"The present invention is related to stacked semiconductor devices and methods for manufacturing stacked semiconductor devices. 

BACKGROUND 

Packaged semiconductor devices are utilized in cellular phones（携帯電話）, pagers, personal digital assistants, computers and many other types of consumer or industrial electronic products. Microelectronics manufacturers are developing more sophisticated（高性能）devices in smaller sizes. To meet current design criteria, semiconductor components have increasingly dense arrays of input/output terminals within decreasing "footprints" on printed circuit boards (i.e. the height and surface area the device occupies on a printed circuit board). Semiconductor devices are typically fabricated on semiconductor wafers or other types of workpieces（ワークピース；＊加工対象物、被加工物）using methods that simultaneously process a large number of dies (i.e., chips). Microelectronic devices generally have a die that includes an integrated circuit having a high density of very small components. The dies typically include an array of bond-pads or other external electrical terminals for transmitting supply voltage, signals, etc. to and from（やり取り）the integrated circuitry. The bond-pads are usually very small and are assembled in dense arrays having fine pitches between bond-pads.

One technique to increase the density of microelectronic devices within a given footprint is stacking（積層）one microelectronic die on top of another. Through-substrate interconnects（基板を介する相互接続）, for example, can electrically connect bond pads at a front side（前面）of a lower die with contacts at a back side（裏面）of the lower die such that bond pads of a top die can be electrically coupled to（結合；＊何かを介して、cf. connect）the back side contacts of the lower die. An existing process for stacking such dies includes thinning（薄層化）first and second wafers by removing material from the back side of the wafers to (1) expose interconnect contact points on the back side of the dies, and (2) reduce the thickness of the dies. The second wafer is generally thinned to not less than（少なくとも；＊以上）300 microns. After thinning, the second wafer is singulated（単一化）(i.e., cut) and separate dies from the second wafer are stacked onto（上に積層）dies on the first wafer. An encapsulant（カプセル化材）is subsequently disposed between individual second dies, and the first wafer and encapsulant are cut to separate stacked devices（切断されて、積層デバイスを分離）."