英語Wikipedia、素晴らしすぎる。
どうもタイミングを示した記号らしい。
DDR3だと
”E”(or”P”)がECC（エラー訂正符号付きアンバッファード）、
”R”がECC-R（エラー訂正符号付きレジスタード）、
”U”（or”記号なし”）がUnBuffered（いわゆる”普通の”メモリ）
だったので、うっかり混同するとエライことに。
JEDEC standard DDR4 module[57][edit]
| Standard name | Memory clock (MHz) | I/O bus clock (MHz) | Data rate (MT/s) | Module name | Peak trans- fer rate (MB/s) | Timings CL-tRCD-tRP | CAS latency (ns) |
|---|---|---|---|---|---|---|---|
| DDR4-1600J* DDR4-1600K DDR4-1600L |
200 | 800 | 1600 | PC4-12800 | 12800 | 10-10-10 11-11-11 12-12-12 |
12.5 13.75 15 |
| DDR4-1866L* DDR4-1866M DDR4-1866N |
233.33 | 933.33 | 1866.67 | PC4-14900 | 14933.33 | 12-12-12 13-13-13 14-14-14 |
12.857 13.929 15 |
| DDR4-2133N* DDR4-2133P DDR4-2133R |
266.67 | 1066.67 | 2133.33 | PC4-17000 | 17066.67 | 14-14-14 15-15-15 16-16-16 |
13.125 14.063 15 |
| DDR4-2400P* DDR4-2400R DDR4-2400T DDR4-2400U |
300 | 1200 | 2400 | PC4-19200 | 19200 | 15-15-15 16-16-16 17-17-17 18-18-18 |
12.5 13.32 14.16 15 |
| DDR4-2666T DDR4-2666U DDR4-2666V DDR4-2666W |
333.33 | 1333.33 | 2666.67 | PC4-21333 | 21333.33 | 17-17-17 18-18-18 19-19-19 20-20-20 |
12.75 13.50 14.25 15 |
| DDR4-2933V DDR4-2933W DDR4-2933Y DDR4-2933AA |
366.67 | 1466.67 | 2933.33 | PC4-23466 | 23466.67 | 19-19-19 20-20-20 21-21-21 22-22-22 |
12.96 13.64 14.32 15 |
| DDR4-3200W DDR4-3200AA DDR4-3200AC |
400 | 1600 | 3200 | PC4-25600 | 25600 | 20-20-20 22-22-22 24-24-24 |
12.5 13.75 15 |
- CAS latency (CL)
- Clock cyclesbetween sending a column address to the memory and the beginning of the data in response
- tRCD
- Clock cycles between row activate and reads/writes
- tRP
- Clock cycles between row precharge and activate
DDR4-xxxx denotes per-bit data transfer rate, and is normally used to describe DDR chips. PC4-xxxxx denotes overall transfer rate, in megabytes per second, and applies only to modules (assembled DIMMs). Because DDR4 memory modules transfer data on a bus that is 8 bytes (64 data bits) wide, module peak transfer rate is calculated by taking transfers per second and multiplying by eight.