IEEE micro, January/February 2006 特集紹介

IEEE micor, January/February 2006 (Vol. 26, No. 1) の特集の紹介
　http://csdl2.computer.org/persagen/DLAbsToc.jsp?resourcePath=/dl/mags/mi/&toc=comp/mags/mi/2006/01/m1toc.xml

Micro's Top Picks from Microarchitecture Conferences
　Guest Editor's Introduction: Micro's Top Picks from Microarchitecture Conferences
　　Josep Torrellas, University of Illinois, Urbana-Champaign.
　　http://doi.ieeecomputersociety.org/10.1109/MM.2006.14
　80編のアブストラクト (3ページ) から 25人の審査員によって選ばれた 13編：
　　Processor and memory architecures for high performance
　　　"Efficient Runahead Execution: Power-Efficient Memory Latency Tolerance",
　　　　　Onur Mutlu, Hyesoon Kim and Yale N. Patt, University of Texas at Austin.
　　　　　http://doi.ieeecomputersociety.org/10.1109/MM.2006.10
　　　"Adaptive History-Based Memory Schedulers for Modern Processors",
　　　　　Ibrahim Hur, IBM Corp. and The University of Texas at Austin and Calvin Lin, The University of Texas at Austin.
　　　　　http://doi.ieeecomputersociety.org/10.1109/MM.2006.1
　　　　　※[06/03/31]
　　　　　　Power5の DRAM(主記憶)メモリーコントローラで採用された "Adaptive History-Based Memory Scheduler" の解説
　　　　　　"This article describes a new memory scheduling approach that makes decisions based on the history of
　　　　　　 recently scheduled operations. When compared with an in-order scheduler, our solution improves
　　　　　　 instruction per cycle (IPC) on the NASA Advanced Supercomputing (NAS) benchmarks by a geometric
　　　　　　 mean of 10.9 percent, and it improves IPC on the Stream benchmarks by more than 63 percent."
　　　　　　トランジスターの増分は 0.04パーセントとのこと。
　　　"Scalable Load and Store Processing in Latency-Tolerant Processors",
　　　　　Amit Gandhi, et al., Intel Corp.
　　　　　http://doi.ieeecomputersociety.org/10.1109/MM.2006.21
　　　"Tolerating Cache-Miss Latency with Multipass Pipelines",
　　　　　Ronald D. Barnes, George Mason University, Shane Ryoo and Wen-mei W. Hwu, University of Illinois, Urbana-Champaign.
　　　　　http://doi.ieeecomputersociety.org/10.1109/MM.2006.25
　　　"Wish Branches: Enabling Adaptive and Aggressive Predicated Execution",
　　　　　Hyesoon Kim, Onur Mutlu, Yale N. Patt, University of Texas at Austin and Jared Stark, Intel.
　　　　　http://doi.ieeecomputersociety.org/10.1109/MM.2006.27
　　Multiprocessing and multithreading
　　　"Unbounded Transactional Memory",
　　　　　C. Scott Ananian, Massachusetts Institute of Technology, et al., and Sean Lie, Advanced Micro Devices.
　　　　　http://doi.ieeecomputersociety.org/10.1109/MM.2006.26
　　　"Coarse-Grain Coherence Tracking: RegionScout and Region Coherence Arrays",
　　　　　Jason F. Cantin, University of Wisconsin-Madison, et al.
　　　　　http://doi.ieeecomputersociety.org/10.1109/MM.2006.8
　　　"Energy-Efficient Thread-Level Speculation",
　　　　　Jose Renau, University of California at Santa Cruz, et al.
　　　　　http://doi.ieeecomputersociety.org/10.1109/MM.2006.11
　　Security and hardware or software robustness
　　　"Opportunistic Transient-Fault Detection",
　　　　　Mohamed A. Gomaa, Purdue University and T. N. Vijaykumar, Purdue University.
　　　　　http://doi.ieeecomputersociety.org/10.1109/MM.2006.20
　　　"BugNet: Recording Application-Level Execution for Deterministic Replay Debugging",
　　　　　Satish Narayanasamy, et al., University of California, San Diego.
　　　　　http://doi.ieeecomputersociety.org/10.1109/MM.2006.7
　　　"Architectures for Bit-Split String Scanning in Intrusion Detection",
　　　　　Lin Tan, University of Illinois, Urbana-Champaign and Timothy Sherwood, University of California, Santa Barbara.
　　　　　http://doi.ieeecomputersociety.org/10.1109/MM.2006.5
　　Envergy and temperature issues
　　　"Dynamic-Compiler-Driven Control for Microprocessor Energy and Performance",
　　　　　Qiang Wu, Princeton University, et al.
　　　　　http://doi.ieeecomputersociety.org/10.1109/MM.2006.9
　　　"Temperature-Aware On-Chip Networks",
　　　　　Li Shang, Queen's University, et al.
　　　　　http://doi.ieeecomputersociety.org/10.1109/MM.2006.23