DesignLineサイト (CMP Media LLC ) 解説記事メモ, II

関連エントリー：
　DesignLineサイト (CMP Media LLC ) 解説記事メモ, Part I, 2006-06-22
　DesignLine (Video Imaging, Digital TV) 解説記事メモ, I, 2006-08-03
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Network Systems DesignLine
　http://www.networksystemsdesignline.com/

[06/08/25]
"IP Resilient Network Fundamentals--Part II",Kok-Keong Lee, Fung Lim, Beng-Hui Ong, Cisco Systems, Network Systems Designline, 08/21/2006
　http://www.networksystemsdesignline.com/192202366
　"'Building Resilient IP Networks,' Chapter 3 covers the Fundamentals of IP Resilient Networks.
　 This segment concentrates on device-level resiliency. Subsequent parts, also featured on
　 Network Systems DesignLine, will cover the impact of different switching paths, and the key principles
　 of designing resilient networks. "
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[06/08/17]
"IP Resilient Network Fundamentals--Part I", Kok-Keong Lee, Fung Lim, Beng-Hui Ong, Cisco Systems, Network Systems Designline, 08/16/2006
　http://networksystemsdesignline.com/192201189
　"Here is a multiple-part series from 'Building Resilient IP Networks.' Chapter 3 covers the
　 Fundamentals of IP Resilient Networks begins with revisiting IP, TCP, and UDP. Subsequent parts,
　 also featured on Network Systems DesignLine, will cover device-level resiliency, the impact of
　 different switching paths, and the key principles of designing resilient networks. "
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Programmable Logic DesignLine
　http://www.pldesignline.com/

[06/08/25]
"A tutorial on incremental design using FPGAs from Actel", Fred Wickersham, Actel, Programmable Logic DesignLine, 08/23/2006
　http://www.pldesignline.com/192203516
　"An "incremental" design flow is highly desirable with regard to repairing or optimizing parts of
　 the design without disturbing portions that have met their design requirements."
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[06/08/17]
"FPGA Architectures from 'A' to 'Z' : Part 1", Programmable Logic DesignLine
, 08/15/2006
　http://www.pldesignline.com/192200165
　"If you are new to FPGAs, there are a bewildering number of different architectures and related concepts;
　 but fear not, because this tutorial explains all."
"How to accelerate algorithms by automatically generating FPGA coprocessors", Programmable Logic DesignLine, 08/09/2006
　http://www.pldesignline.com/191900750
　"Recent advances in C-to-FPGA design methodologies and tools facilitate the rapid creation of
　 hardware-accelerated embedded systems."
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DSP DesignLine
　http://www.dspdesignline.com/

[06/08/17]
"Unite algorithm and hardware design flows", DSP DesignLine, 07/24/2006
　http://www.dspdesignline.com/191000406
　"Past attempts to bridge between the DSP design domain and physical implementations fell short,
　 but the new "DSP synthesis" approach creates a truly integrated design flow."
"Designing control circuits for FPGA-based DSP systems", DSP DesignLine, 08/11/2006
　http://www.dspdesignline.com/191800731
　"Need to design a control circuit for your FPGA-based DSP system? These simple techniques
　 could save you days of work. Topics covered include data-driven multiplexing, finite state machines,
　 sample rate control, pattern generation, and low-rate control algorithms."
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Power Management DesignLine
　http://www.powermanagementdesignline.com/