RAMP:ResearchAccelerator4 MultipleProcessors, FPGA

RAMP - Research Accelerator for Multiple Processors
　UC Berkeleyを中心とした、FPGAを利用した新たな大規模並列処理研究用プラットホーム開発ロジェクト：

"A 1,000-processor computer for $100K?", CNET News.com, February 24, 200
　http://news.com.com/A+1%2C000-processor+computer+for+100K/2100-1010_3-6042849.html?tag=cd.top
　"Enter RAMP, or Research Accelerator for Multiple Processors. The idea behind
　 the program is to build a laboratory computer out of field programmable gate arrays,
　 reprogrammable chips that can be reconfigured to act as different chips."


RAMP - Research Accelerator for Multiple Processors
　http://ramp.eecs.berkeley.edu/
残念ながら具体的な資料は未だ一般には公開されていません。
上記 CNET News.comで
　""If you can put 25 CPUs in one FPGA, you can put 1,000 CPUs in 40 FPGAs,"
　 Patterson said during a symposium here this week at UC Berkeley, where he is
　 a professor of electrical engineering. Such a computer would cost about $100,000,
　 he estimated."
紹介されている、以下のシンポジウムの Patterson教授の資料
　2006 Berkeley EECS Annual Research Symposium (BEARS)
　　http://www.eecs.berkeley.edu/BEARS/
　　"The Future of Computer Architecture", David Patterson (PPT, Webcast)
に概略が説明されています。また以下のプロポーザルが公開されています：
"RAMP: Research Accelerator for Multiple Processors
　- A Community Vision for a Shared Experimental Parallel HW/SW Platform",
　　Arvind (MIT), Krste Asanovic (MIT), Derek Chiou (UT Austin), James C. Hoe (CMU),
　　Christoforos Kozyrakis (Stanford), Shih-Lien Lu (Intel), Mark Oskin (U Washington),
　　David Patterson (UC Berkeley), Jan Rabaey (UC Berkeley), and John Wawrzynek (UC Berkeley),
　　Technical Report No. UCB/CSD-05-1412, EECS Department, University of California, Berkeley, 2005
　　http://www.eecs.berkeley.edu/Pubs/TechRpts/2005/6513.html
　1 Overview
　"We propose to build and support a large-scale, FPGA-based emulation platform to accelerate
　 research in multiprocessors. Advances in FPGA capacity and speed now enable a 1024-processor
　 system to be emulated with just a few dozen FPGAs at very low cost per processor. By creating
　 a research community around a common hardware and software infrastructure, we will pool
　 our resources to build a far more productive environment than we could have achieved individually.
　 Hence the name of the system, Research Accelerator for Multiple Processors (RAMP), as it should
　 ramp up the rate of research in hardware and software for multiple processors. This report is
　 the text of a proposal to NSF to support the development of RAMP."

キーワードは "large-scale, FPGA-based emulation platform" です。
RAMPを新たな大規模並列処理研究のプラットフォームにしていこう、との提案です。
ストレージに関しては次のように言及しています
　2.3 Emulation Methodologies
　"Rather than put disks on the same boards as the FPGAs, our plan is to use a seperate, network
　 attached storage device (NASD) using either the Infiniband links or the 10 Gbit Ethernet links.
　 Using such an off-the-shelf storage array should dramtically simplify the design and management of
　 RAMP. We would use a virtual machine such as Xen running on each processor to present a simple,
　 single, large virtual disk to each operating system. The NASD could then act as a block server to
　 each VM, likely running on top of a file system in order to simplify management."

　NAS (Network Attached Storage) ではなく Network Attached Storage Device (NASD) に注目。
　当然ながら、ファイルシステムも研究対象だから、Blockデバイスである必要があるのでしょう。
　Network Attached Storage Device(NASD)の考えは Object Storage Device (OSD) に影響を与えました。
　関連エントリー：
　　IBM Object Storage Device Simulator for Linux, 2006-02-24


RAMP Principal Investigators (PAMPでやろうとしていることの一例)
　Arvind (MIT)：ラストネームだけだそうです
　　http://csg.csail.mit.edu/Users/arvind/
　　　UNUM: A tinker-toy approach to building PowerPC microarchitectures
　Krste Asanovic (MIT)
　　http://cag.csail.mit.edu/~krste/
　　　Scalable Multithreaded Architectures
　Derek Chiou (UT Austin)
　　http://www.ece.utexas.edu/~derek/
　　　Network processors
　James C. Hoe (CMU)
　　http://www.ece.cmu.edu/~jhoe/
　　　Fault-tolerant Systems
　Christoforos Kozyrakis (Stanford)
　　http://csl.stanford.edu/~christos/
　　　Research on Multiprocessor Software
　　　Transactional Memory Systems
　Shih-Lien Lu (Intel)
　　http://www.intel.com/technology/techresearch/people/bios/lu_s.htm
　　　Transactional Memory Systems
　Mark Oskin (U Washington)
　　http://www.cs.washington.edu/homes/oskin/
　　　Data-Flow Architectures for C
　David Patterson (UC Berkeley)
　　http://www.cs.berkeley.edu/~pattrsn/
　　　Internet In A Box
　Jan Rabaey (UC Berkeley)
　　http://bwrc.eecs.berkeley.edu/People/Faculty/jan/
　John Wawrzynek (UC Berkeley)
　　http://www.cs.berkeley.edu/~johnw/
　　　Application Specific Accelerators and Architectures

Academic Supportersには TRIPS (The Tera-op, Reliable, Intelligently adaptive Processing System) の
Doug Burger, Steve Keckler両教授、Merrimac (Stanford Streaming Supercomputer Project)：Bill Dally教授、
Unified Parallel Cの Kathy Yelick教授らも参加しています。
　産業界からは、Gordon Bell博士(Microsoft)、Ivo Bolsens博士(Xilinx, CTO)、Ivan Sutherland博士 (Sun)、
Microsoft, Sun, Intel各社の CTO等も名を連ねています。
☆ OpenFPGAとの関係は？？？

プロジェクトは 3年間を提案しています。


RAMP1は、Berkeley Wireless Research Center (BWRC)で開発された BEE 2 (Berkeley Emulation Engine) 2
を採用するそうです(RAM2まで計画)。BEE 2(すでに開発済み) については別エントリーとします。
　Berkeley Emulation Engine(BEE)2, FPGA採用研究環境, 2006-02-26


少し関連エントリー：
　Computer News/メモ, 06/03/07
　　"Intel CTO tips 'tera-scale' computing ", EE Times, 03/06/2006
　　　Transactional memoryに言及しています。


※[06/03/19]
RAMP - Publications and Documents
　http://ramp.eecs.berkeley.edu/publications.php
　各種資料の公開
Wiki
　BEE2 Documentationへのリンク

"RAMP Architecture and Description Language,"
　Greg Gibeling and Andrew Schultz, U.C. Berkeley, and Krste Asanovic, MIT
　RAMP Special Session
　　2nd Workshop on Architecture Research using FPGA Platforms (WARFP-2006)
　　http://cag.csail.mit.edu/warfp2006/program.html
　Held in conjunction with the
　12th International Symposium on High-Performance Computer Architecture (HPCA-12), February 12, 2006.


追加情報
　OpenSPARC T1 Release 1.0 March 21, 2006 & RAMP, 2006-03-22