DesignLineサイト (CMP Media LLC ) 解説記事メモ, Part I

DesignLineサイト (CMP Media LLC ) 解説記事メモ, II, 2006-08-18
===================
関連エントリー：
　DesignLine (Video Imaging, Digital TV) 解説記事メモ, I, 2006-08-03
=====
Network Systems DesignLine
　http://www.networksystemsdesignline.com/

[06/08/10]
"Maneuver the next-gen backplane maze", Courtesy of embedded.com, 07/05/2006
　http://www.networksystemsdesignline.com/190300160

"12-port switch takes RapidIO from the local interconnect to the backplane", Courtesy of eeProductCenter, 08/01/2006
　http://www.networksystemsdesignline.com/191601524

"High-speed crosspoint switches deliver 900-Gbits/s capacity", eeProductCenter, 08/01/2006
　http://www.eeproductcenter.com/showArticle.jhtml?articleID=191601201

"An Introduction to LAN Switching--Part III", Matthew J. Castelli, Network Systems DesignLine, 08/09/2006
　http://www.networksystemsdesignline.com/191900287
-----
[06/07/27]
"An introduction to LAN switching--Part I", Matthew J. Castelli, Network Systems DesignLine, 07/19/2006
　http://www.networksystemsdesignline.com/190600077
　LAN Switching first-step, Matthew J. Castelli: Chapter 6: How a Switch Works. Published by Cisco Press
　"This excerpt from Chaper 6 of LAN Switching first-step--How a switch works--covers unicast, multicast
　 and broadcast transmission methods and describes such concepts as store-and-forward, cut through,
　 and fragment-free switching."
"An introduction to LAN switching--Part II", Matthew J. Castelli, Network Systems DesignLine, 07/26/2006
　http://www.networksystemsdesignline.com/191200526
-----
[06/06/29]
"Scale network processors to 40 Gbps and beyond", Network Systems DesignLine, 06/28/2006
　http://www.networksystemsdesignline.com/189602236
-----
"10GBASE-T: 10G Ethernet on copper cabling--Part I", Network Systems DesignLine, 03/22/2006
　　http://www.networksystemsdesignline.com/183701720
"10GBASE-T: 10G Ethernet on copper cabling--Part II", Network Systems DesignLine, 03/29/2006
　　http://www.networksystemsdesignline.com/184400885
"10G LAN PHY to 10G WAN PHY protocol converter stands alone", Network Systems DesignLine, 05/31/2006
　　http://www.networksystemsdesignline.com/188700526
"Fast Ethernet to GbE migration drives massive Ethernet switch upgrade", Network Systems DesignLine, 04/24/2006
　　http://www.networksystemsdesignline.com/186700266
"How to optimize switch design for next-generation Ethernet networks", Network Systems DesignLine, 06/14/2006
　　http://www.networksystemsdesignline.com/189401062
　　　IEEE 802.3an: 10GBase-T規格承認, 06/06/08 (消費電力考), 2006-06-17

"Extend SAN over WDM, SONET/SDH, or IP--Part I", Network Systems DesignLine, 05/15/2006
　　http://www.networksystemsdesignline.com/187202957
"Extend SAN over WDM, SONET/SDH, or IP--Part II", Network Systems DesignLine, 05/19/2006
　　http://www.networksystemsdesignline.com/188100436

"Balance load and customize content at Layer 7--A tutorial--Part I", Network Systems DesignLine, 04/26/2006
　　http://www.networksystemsdesignline.com/186701128
"Balance load and customize content at Layer 7--A Tutorial: Part II", Network Systems DesignLine, 04/28/2006
　　http://www.networksystemsdesignline.com/187001253
"Balance load and customize content at Layer 7--Part III", Network Systems DesignLine, 05/03/2006
　　http://www.networksystemsdesignline.com/187200003

"Design for network convergence", Network Systems DesignLine, 05/08/2006
　　http://www.networksystemsdesignline.com/187201097

"Start your crypto engine--cryptographic acceleration in SoCs", Network Systems DesignLine, 04/21/2006
　　http://www.networksystemsdesignline.com/186500462
"Communications and media processors (CMPs) offer less RISC", Network Systems DesignLine, 04/19/2006
　　http://www.networksystemsdesignline.com/186100062

"Serial RapidIO switch targets DSP-intensive processing apps", Network Systems DesignLine, 05/31/2006
　　http://www.networksystemsdesignline.com/188700548

"Too much heat? Implement thermal management", Network Systems DesignLine, 04/17/2006
　　http://www.networksystemsdesignline.com/185303081
=====
Programmable Logic DesignLine
　http://www.pldesignline.com/

"Implementing PCI Express Designs using FPGAs", Programmable Logic DesignLine, 06/07/2006
　　http://www.pldesignline.com/188701927
"How to lower the cost of PCI Express adoption by using FPGAs", Programmable Logic DesignLine, 04/26/2006
　　http://www.pldesignline.com/186701287

"Core-assisted approach accelerates debug of FPGA DDR II interfaces", Programmable Logic DesignLine, 06/21/2006
　　http://www.pldesignline.com/189600434

"Using FPGA partial reconfiguration capability to mitigate design variability", EE Times, 04/03/2006
　　http://www.pldesignline.com/184428547
=====
DSP DesignLine
　http://www.dspdesignline.com/

[06/07/25]
"Optimizing for cache performance, part 1", Jackie Brenner, Senior Member of Technical Staff, TI, DSP DesignLine, 07/04/2006
　http://www.dspdesignline.com/190300015
　"Learn how caches work and what causes cache misses"
"Optimizing for cache performance, part 2", Jackie Brenner, Senior Member of Technical Staff, TI, DSP DesignLine, 07/10/2006
　http://www.dspdesignline.com/190300078
　"Good planning can prevent cache misses and improve performance"
-----
"Virtex-5 features DSP enhancements", DSP DesignLine, 06/14/2006
　　http://www.dspdesignline.com/189400956

"Design and verification strategies for complex systems, part 1", DSP DesignLine, 05/29/2006
　　http://www.dspdesignline.com/188703479
"Design and verification strategies for complex systems, part 2", DSP DesignLine, 06/19/2006
　　http://www.dspdesignline.com/189500144

"21st century multiprocessor design, part 1", DSP DesignLine, 05/29/2006
　　http://www.dspdesignline.com/188500816
"21st century multiprocessor design, part 2", DSP DesignLine, 06/04/2006
　　http://www.dspdesignline.com/188701424
=====
Power Management DesignLine
　http://www.powermanagementdesignline.com/

[06/07/25]
"How to provide a power-efficient architecture", Bob Crepps, Intel Corp., Power Management DesignLine, 07/24/2006
　http://www.powermanagementdesignline.com/191000290
　"It's anything but a smooth ride for processors with many challenges including the amount of energy consumed
　 per logic operation. Here's what can be done to reduce total power consumption."
-----
"How to integrate intelligent thermal management into a CPU fan", Power Management DesignLine, 05/03/2006
　　http://www.powermanagementdesignline.com/187003251