気になる AMD公開特許情報 (AMD US Patents)

関連 Webニュース (日本語だけにします)
　PC Watch: 後藤弘茂のWeekly海外ニュース
　　"Rev. Fの次の次に来るAMDの次世代コア「Hound」", 2006年 5月 31日
　　　http://pc.watch.impress.co.jp/docs/2006/0531/kaigai273.htm
　　"AMDがK8コアの浮動小数点演算ユニットを2倍に
　　　～Rev. Hと見られるCPUコアの姿を公開", 2006年5月22日
　　　http://pc.watch.impress.co.jp/docs/2006/0522/kaigai272.htm
　　"クアッドコアCPUを2段階投入するAMDのロードマップ", 2006年 5月 3日
　　　http://pc.watch.impress.co.jp/docs/2006/0503/kaigai267.htm
　　"CPUコアの設計が一新される65nm版K8", 2006年 4月 24日
　　　http://pc.watch.impress.co.jp/docs/2006/0424/kaigai263.htm
　　"ヘテロジニアスマルチコアも視野に入れたAMD", 2006年 1月 30日
　　　http://pc.watch.impress.co.jp/docs/2006/0130/kaigai237.htm
　PC Watch: Spring Processor Forum 2006レポート, 大原雄介
　　"クアッドコアOpteronの詳細", 2006年 5月 19日
　　　http://pc.watch.impress.co.jp/docs/2006/0519/spf03.htm
　日経 BP Tech On!, 枝 洋樹＝日経エレクトロニクス
　　"【SPF速報】AMD社が語る次世代86系マイクロプロセサの設計思想", 2006/05/17
　　　http://techon.nikkeibp.co.jp/article/NEWS/20060517/117171/

※[06/06/01]
　PC Watch: 後藤弘茂のWeekly海外ニュース
　　"拡大が進むAMDのコプロセッサ構想", 2006年 6月 1日
　　　http://pc.watch.impress.co.jp/docs/2006/0601/kaigai275.htm


ここ最近公開された AMD特許情報で、名称が気になるものと話題になった特許のメモ
Assigneeは全て Advanced Micro Devices, Inc. (Sunnyvale, CA)
米国特許番号、特許名称、出願日、公開日：

US Patent 6944744: "Apparatus and method for independently schedulable functional units with issue lock mechanism in a processor", 2002-08-27, 2005-09-13.
US Patent 7003629: "System and method of identifying liveness groups within traces stored in a trace cache", 2003-07-08, 2006-02-21.
US Patent 7006943: "Method and apparatus for using an on-board temperature sensor on an integrated circuit", 2000-09-12, 2006-02-28.
US Patent 7009618: "Integrated I/O Remapping mechanism", 2002-04-30, 2006-03-07.
US Patent 7015078: "Silicon on insulator substrate having improved thermal conductivity and method of its formation", 2003-09-09, 2006-03-21.
US Patent 7023445: "CPU and graphics unit with shared cache", 2004-04-12, 2006-04-04.
US Patent 7024545: "Hybrid branch prediction device with two levels of branch prediction cache", 2001-07-24, 2006-04-04.
US Patent 7030877: "Computer graphics processing system, computer memory, and method of use with computer graphics processing system utilizing hierarchical image depth buffer", 2002-03-04, 2006-04-18.
US Patent 7035983: "System and method for facilitating communication across an asynchronous clock boundary", 2003-04-25, 2006-04-25.
US Patent 7036030: "Computer system and method of using temperature measurement readings to detect user activity and to adjust processor performance", 2002-02-07, 2006-04-25.
US Patent 7039755: "Method and apparatus for powering down the CPU/memory controller complex while preserving the self refresh state of memory in the system", 2000-05-31, 2006-05-02.
US Patent 7039819: "Apparatus and method for initiating a sleep state in a system on a chip device", 2003-04-30, 2006-05-02.
US Patent 7043593: "Apparatus and method for sending in order data and out of order data on a data bus", 2003-04-29, 2006-05-09.
US Patent 7043616: "Method of controlling access to model specific registers of a microprocessor", 2003-04-18, 2006-05-09.
US Patent 7043626: "Retaining flag value associated with dead result data in freed rename physical register with an indicator to select set-aside register instead for renaming", 2003-10-01, 2006-05-09.
US Patent 7043679: "Piggybacking of ECC corrections behind loads", 2002-06-27, 2006-05-09.


関連エントリー：
　Horus：AMD Opteron大規模サーバ用 (max 32CPU) チップ, 2006-01-16
Assignee: Newisys, Inc.

US Patent 6920532: "Cache coherence directory eviction mechanisms for modified copies of memory lines in multiprocessor systems", 2002-11-05, 2005-07-19.
US Patent 6925536: "Cache coherence directory eviction mechanisms for unmodified copies of memory lines in multiprocessor systems", 2002-11-05, 2005-08-02.
US Patent 6934814: "Cache coherence directory eviction mechanisms in multiprocessor systems which maintain transaction ordering", 2002-11-05, 2005-08-23.
US Patent 7024521: "Managing sparse directory evictions in multiprocessor systems via memory locking", 2003-04-24, 2006-04-04.
US Patent 7039740: "Interrupt handling in systems having multiple multi-processor clusters", 2002-07-19, 2006-05-02.
US Patent 7047372: "Managing I/O accesses in multiprocessor systems", 2003-04-15, 2006-05-16.