announce@opensparc.sunsource.net
Date: Thu, 18 May 2006 09:12:47 -0700
Subject: OpenSPARC T1 version 1.1 released!
http://opensparc.sunsource.net/servlets/ReadMsg?list=announce&msgNo=10
Welcome to OpenSPARC.net
http://opensparc.sunsource.net/nonav/index.html
New items available with Version 1.1 are:
Source code for the Hypervisor
SAM/Legion enhancements to copy files to/from simulated disk
Notes and scripts to enable an FPGA implementation of parts of OpenSPARC T1 design including SPARC core, Floating point Unit, Cross-bar.
New FPGA project started so that experts can join and shared their efforts with the community.
特に興味をひかれるのが、"New FPGA project started"
OpenSPARC T1: FPGA Implementation
http://fpga.sunsource.net/index.html
Chip Design and Verification Download Package Version 1.1 includes:
Scripts to run Synplicity software to map RTL into FPGA for the following blocks in OpenSPARC T1:
o SPARC CPU core
o FPU - Floating Point Unit
o CCX - CPU/Cache Cross bar
Synthesizable Verilog SRAMs modules for the SRAMs used in above blocks.
You can select FPGA of your choice: Xilinx, Altera, etc.
関連エントリーの一部
OpenSPARC T1 Release 1.0 March 21, 2006 & RAMP, 2006-03-22
Date: Thu, 18 May 2006 09:12:47 -0700
Subject: OpenSPARC T1 version 1.1 released!
http://opensparc.sunsource.net/servlets/ReadMsg?list=announce&msgNo=10
Welcome to OpenSPARC.net
http://opensparc.sunsource.net/nonav/index.html
New items available with Version 1.1 are:
Source code for the Hypervisor
SAM/Legion enhancements to copy files to/from simulated disk
Notes and scripts to enable an FPGA implementation of parts of OpenSPARC T1 design including SPARC core, Floating point Unit, Cross-bar.
New FPGA project started so that experts can join and shared their efforts with the community.
特に興味をひかれるのが、"New FPGA project started"
OpenSPARC T1: FPGA Implementation
http://fpga.sunsource.net/index.html
Chip Design and Verification Download Package Version 1.1 includes:
Scripts to run Synplicity software to map RTL into FPGA for the following blocks in OpenSPARC T1:
o SPARC CPU core
o FPU - Floating Point Unit
o CCX - CPU/Cache Cross bar
Synthesizable Verilog SRAMs modules for the SRAMs used in above blocks.
You can select FPGA of your choice: Xilinx, Altera, etc.
関連エントリーの一部
OpenSPARC T1 Release 1.0 March 21, 2006 & RAMP, 2006-03-22