Product Operation CLOCK and Knowledge TRANSITIONS

The SDA pin is generally pulled higher by having an exter- nal machine. Information within the SDA pin may change only all through SCL low time periods (check with Details Validity timing diagram). Info changes all through SCL higher intervals will indicate a start out or stop problem as defined below.

Start out Situation: A high-to-low transition of SDA with SCL higher is usually a start off issue which must precede almost every other command (confer with Begin and Cease Definition timing diagram).

Stop Issue: A low-to-high changeover of SDA with SCL large is a stop affliction. Following a examine sequence, the quit command will location the EEPROM in a very standby ability manner (check with Get started and End Definition timing diagram).

Admit: All addresses and info words are serially transmitted to and in the EEPROM in eight bit words. The EEPROM sends a zero to acknowledge that it's got received each and every phrase. This happens throughout the ninth clock cycle.

STANDBY Mode: The AT24C02A/04A/08A/16A features a lower ability standby manner that's enabled: (a) on power-up and (b) immediately after the receipt of the End little bit as well as the completion of any inside operations.

MEMORY RESET: Right after an interruption in protocol, electrical power decline or technique reset, any 2-wire portion could be reset by next these actions: (a) Clock up to 9 cycles, (b) seem for SDA large in just about every cycle whilst SCL is higher after which you can (c) produce a start out affliction as SDA is superior.

The sign up will take out the examine information on the info output pin

The AK6420A/40A/80A can be a 2048/4096/8192bit, serial, read/write, non-volatile memory system fabricated utilizing anadvanced CMOS EEPROM engineering. The AK6420A has 2048bits of memory structured into 128 registers of 16bits just about every.

The AK6440A has 4096bits of memory structured into 256 registers of sixteen bits each and every.

The AK6480A has8192bits of memory organized into 512 registers of 16 bits every. The AK6420A/40A/80A can function comprehensive functionunder huge working voltage range from 1.8V to 5.5V.

The cost up circuit is built-in for top voltage generationthat is utilised for generate operation.The AK6420A/40A/80A can hook up with the serial conversation port of well-liked a person chip microcomputer specifically (3line destructive clock synchronous interface).

At create procedure, AK6420A/40A/80A requires in the publish details from datainput pin (DI) to the sign up synchronously with increasing fringe of enter pulse of serial clock pin (SK).

And at examine procedure,AK6420A/40A/80A can take out the browse information from a sign-up to knowledge output pin (DO) synchronously with falling edge ofSK.The AK6420A/40A/80A has four instructions this kind of as Examine, Produce, WREN (write allow) and WRDS (write disable).Each instruction is organized by op-code block (8bits), deal with block (8bits) and details (8bits × two).

When input amount ofSK pin is higher level and enter level of chip pick (CS) pin is changed from substantial amount to lower amount, AK6420A/40A/80Acan obtain the guidance.

Two-way pins are used to transfer addresses and data to devices and data

　　The descriptions of the pins are listed in Table 7-1.TABLE 7-1: PIN FUNCTION TABLE7.1 A0, A1, A2 Chip Address InputsThe A0, A1, A2 inputs are used by the 24XX64 for mul-tiple device operation.

　　The levels on these inputs arecompared with the corresponding bits in the slaveaddress.

　　The chip is selected if the compare is true.Up to eight devices may be connected to the same busby using different chip select bit combinations. Theseinputs must be connected to either VCC or VSS.

　　7.2 Serial Data (SDA)This is a bi-directional pin used to transfer addressesand data into and data out of the device. It is an open-drain terminal, therefore, the SDA bus requires a pull-up resistor to VCC (typical 10 k? for 100 kHz, 2 k? for400 kHz)For normal data transfer SDA is allowed to change onlyduring SCL low.

　　Changes during SCL high arereserved for indicating the START and STOP condi-tions.7.3 Serial Clock (SCL)This input is used to synchronize the data transfer fromand to the device.7.4 Write Protect (WP)This pin can be connected to either VSS, VCC or leftfloating.

　　An internal pull-down resistor on this pin willkeep the device in the unprotected state if left floating.If tied to VSS or left floating, normal memory operationis enabled (read/write the entire memory 0000-1FFF).If tied to VCC, WRITE operations are inhibited. Readoperations are not affected.