Z-RAM, Niagara2, Tulsa at HOT CHIPS 18, Aug. 2006

[06/09/29]
Niagara II 関連リンク, 2006-09-25
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[06/09/12]
Niagara II, Real World Technologies, 06/09/04, 2006-09-08
　HOT CHIPS 18プレゼンテーション発表者の Sun Microsystems Distinguished Engineer Greg Grohoski
　(Gregory F. Grohoski) 氏の職歴を追加
==========
[06/09/06]
"Niagara-2: A Highly Threaded Server-on-a-Chip", Greg Grohoski, 22 August 2006
　http://www.opensparc.net/publications/presentations/niagara-2-a-highly-threaded-server-on-a-chip.html
HOT CHIPS 18で発表された、Niagara2のプレゼンテーション資料の公開 (PDF)
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[06/08/25]
"Intel CTO: multicore performance standards needed", EE Times, 08/24/2006
　http://www.eet.com/news/latest/showArticle.jhtml?articleID=192204967
　"In a keynote presentation at this week's IEEE Hot Chips Conference at Stanford University, Rattner noted
　 that designers must deal with complex memory hierarchies and sophisticated on-chip interconnect fabrics
　 to ensure the cores are not data starved. At the same time, the processor must provide explicit thread
　 support and deal with time-critical functions, as well as include fixed-function accelerators."
　　Intel supports University education Multi-Core, August, 2006, 2006-08-25

"サンの「Niagara II」、マルチスレッド処理の方向性を一段と明確に", CNET Japan, 2006/08/24
　http://japan.cnet.com/news/ent/story/0,2000056022,20211827,00.htm
　"カリフォルニア州パロアルト発--Sun Microsystemsのエンジニアが米国時間8月22日に語ったところによると、
　 2007年後半にサーバ市場への投入が予定されている同社の次期プロセッサ「Niagara II」は、初代Niagara
　 （正式名称「UltraSPARC T1」）の2倍となる64個の命令シーケンスを同時処理できるようになるという。"
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[06/08/23]
The Registerの速報ということで：
"CMU promises to fix speech recognition with a chip", The Register, 22nd August 2006
　http://www.reghardware.co.uk/2006/08/22/cmu_speech_chip/
　"Hot Chips Speech technology ranks right down there with flying cars, robots and Windows as the grandest of
　 disappointments in geekdom. Thankfully, the horrid state of the technology hasn't broken the will of
　 all researchers in the speech field."
"Geeks pray $100,000 box will solve software crisis", The Register, 22nd August 2006
　http://www.theregister.co.uk/2006/08/22/ramp_mit_fix/
　"Hot Chips There's a weird 1,000-processor computer floating about that's being hailed as the "MIT Fix.""
"Intel begs for multi-threaded software aid", The Register, 22nd August 2006
　http://www.theregister.co.uk/2006/08/22/intel_suite_help/
　"Hot Chips Long used to hawking GHz above all else, Intel has found the transition to a multi-core world with
　 flat clock rates painful. The multi-core shift has, in fact, become so difficult that Intel is looking to partners
　 for help designing and evaluating its future products."
"Sun confirms all about 64-thread Niagara II", The Register, 22nd August 2006
　http://www.theregister.co.uk/2006/08/22/sun_niagaratwo/
　"Hot Chips Sun Microsystems will later today reveal the inner goo behind its Niagara II processor –
　 the second chip in the company's "radical" multi-core line."
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[06/08/22]
"Hot Chips hosts high-performance architecture", EE Times, 08/21/2006
　http://www.eeproductcenter.com/showArticle.jhtml?articleID=192202337
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[06/08/19]
8月 20日～22日に開催される HOT CHIPS 18で、Innovative Silicon Inc.(ISi)の Z-RAM、Sun Microsystems, Inc.の Niagara2、
Intel Corp.の Tulsaの発表があります：


HOT CHIPS 18, August 20-22, 2006
　http://www.hotchips.org/hc18/main_page.htm
　August 20, 2006
　　Morning Tutorial (9:00am-12:30pm: )
　　　Presentation: Multicore Programming: From Threads to Transactional Memory
　　Afternoon Tutorial (1:30-5:00pm)
　　　Presentation: Wireless in the Home - Challenges and Opportunities
　August 21, 2006
　　Session One: Video Processing (9:30-11:00am)
　　　Highly Integrated Nexperia PNX8535 Hybrid Television Processor, Philips Semiconductors
　　　Heterogeneous Multiprocessing for Efficient Multi-Standard High Definition Video Decoding, Philips Semiconductors
　　　Home entertainment-quality multimedia experience whilst on the move – Philips Nexperia Mobile Multimedia Co-Processor PNX4103, Philips Semiconductors
　　Keynote I (11:20am-12:20pm)
　　　Cool Codes for Hot Chips
　　　　Authors(s): Justin Rattner, Chief Technology Officer & Intel Senior Fellow, Intel
　　Session Two: Microprocessors I (1:20-2:20pm)
　　　The Low-Power High-Performance Architecture of the PWRficient Processor Family, P.A. Semi
　　　　 P.A. Semi White Paper [05/10/25:オリジナル], 2006-01-07
　　　The Opteron CMP NorthBridge Architecture, Now and in the Future, AMD
　　Session Three: Memory and Storage (2:20-3:20pm)
　　　Z-RAM Ultra-dense Memory for 90nm and Below, Innovative Silicon
　　　　"Innovative Silicon Selected for Upcoming HOT CHIPS Conference; Company to Present on "Z-RAM ultra-dense memory for 90nm and below"", Aug. 10, 2006
　　　　　http://www.embeddedtechjournal.com/news_2006/08/20060810_01.htm
　　　　Innovative Silicon Inc.: http://www.innovativesilicon.com/index.php
　　　　DigiTimes.com: The case for Z-RAM, 06/03/28-31, 2006-03-31
　　　　Computer News/メモ, 06/01/212006-01-21
　　　　　"AMD licenses Innovative Silicon's SOI memory", 01/19/2006
　　　The Ultra Small HDD for the Mobile Applications, Toshiba
　　Session Four: Reconfigurable Computing (3:40-5:10pm)
　　　Virtex5, the Next Generation 65nm FPGA, Xilinx
　　　RAMP: Research Accelerator for Multiple Processors,
　　　　RAMP: ResearchAccelerator4 MultipleProcessors, FPGA, 2006-02-26
　　　An Implementation of Hardware Accelerator using Dynamically Reconfigurable Architecture, Toshiba R&D Center
　　Session Five: Parallel Processing (5:30-7:00pm)
　　　TeraOPS Hardware & Software: A New Massively-Parallel, MIMD Computing Fabric IC, Ambric, Inc.
　　　　http://www.ambric.com/
　　　　"System of hardware objects", United States Application 20050015733
　　　The CA1024: A Fully Programmable System-On-Chip for Cost-Effective HDTV Media Processing, Connex Technology
　　　　http://www.connextechnology.com/
　　　Hardware and Applications of AsAP: An Asynchronous Array of Simple Processors, UC Davis
　　　　Asynchronous Array of Simple DSP, ISSCC 2006, 2006-02-21
　　Panel Discussion: Who Owns the Living Room? (8:00-9:30pm)

　August 22, 2006
　　Session Six: embedded Processors (8:30-10:30am)
　　　ARM996HS: The First Licensable, Clockless 32-bit Processor Core, Handshake Solutions and ARM Ltd.
　　　The MIPS32® 34K™ Processor Cores: Ultimate Design Flexibility for embedded Applications, MIPS
　　　Design of a Reusable 1GHz, Super-scalar ARM Processor, ARM Inc
　　　Towards Optimal Custom Instruction Processors, Imperial College, London
　　Keynote II (10:50-11:50am)
　　　Collaborative Innovation: A New Lever in Information Technology Development
　　　　Authors(s): Bernard Meyerson, IBM Fellow;
　　Session Seven: Novel Silicon Applications (12:50-2:20pm)
　　　In Silico Vox: Towards Speech Recognition in Silicon, Carnegie Mellon University
　　　A Novel Processor Architecture for High-Performance Stream Processing, IBM Research, Zurich
　　　Micro Manipulator Array for Nano-bioelectrics Era, Toshiba R&D Center
　　Session Eight: Communications (2:40-4:10pm)
　　　FocalPoint: A Low-Latency, High-Bandwidth Ethernet Switch Chip, Fulcrum Microsystems
　　　SH-MobileG1: A Single-Chip Application and Dual-mode Baseband Processor, Renesas Technology and NTT DoCoMo
　　　APP300 Access Network Processor, Agere Systems
　　Session Nine: Microprocessors II (4:30-6:30pm)
　　　TULSA, A Dual P4 Core Large Shared Cache Intel® Xeon™ Processor for the MP Server Market Segment, Intel
　　　Niagara2: A Highly-Threaded Server-on-A-Chip, Sun
　　　Blackford: A Dual Processor Chipset for Servers and Workstations, Intel
　　　Inside the Core™ Microarchitecture, Intel
　　Closing Remarks (6:30-6:45pm)
　　　
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しばらくしたらプレゼンテーション資料は公開され、優れた (インパクトのあった) ものは IEEE Microで特集されます：
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　http://www.hotchips.org/archives/
IEEE Micro: Hot Chips17(2005) 特集, March/April 2006, 2006-06-05