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Safety Design Of CPU IP ─ MIPS I6500-F

2017-06-16 16:54:51 | 日記

Imagination Technologies (IMG.L) today announced the availability of a highly scalable 64-bit MIPS multiprocessing solution that has been rigorously evaluated and validated to meet the functional safety (FuSa) requirements of ISO 26262 and IEC 61508. This is an ideal choice for handling their intensive operations, such as automatic driving, industrial IoT and robotic emerging security critical systems. The I6500-F's capabilities extend beyond the other FuSa CPU IP cores to provide a high-performance, high-efficiency foundation for multi-core design of these systems and extend to 64 heterogeneous clusters in one system. Multi-threaded, multi-core MIPS CPU and other accelerators.

FuSa is extremely important for all components in a secure critical system, including the most critical CPU IP in the SoC. Such as automatic driving and intelligent plant industrial control systems and other applications, need more and more processing power, has gone beyond the current compliance with the FuSa standard CPU IP core provided by the function. As a result, customers can take advantage of the scalability of the I6500-F to effectively integrate the ever-increasing number of intelligent features - including artificial intelligence technologies such as CNN and DNN, in their secure critical equipment.So how to recharge cr123a and how to flash nrf51822? That is the same question.

Jim Nicholas, executive vice president of IP, MIPS processor, said: "We can provide a new generation of autonomous and intelligent systems to facilitate the operation of its intensive tasks required for the excellent performance.I6500-F is a fully tested IP solution, To ensure that customers meet the most stringent security requirements.If you are now developing SoC for such systems, the I6500 - F will be your best choice.

Based on the work of the existing MIPS P5600 and other IP cores, Imagination is introducing basic security technologies for the entire MIPS product portfolio. The P5600 has been used in safety-critical designs to support high-reliability industrial environments.

It has also continued Imagination with Mobileye's security technology. Mobileye's EyeQ® 4 SoC for ADAS features MIPS interAptiv and the M5150 CPU with software self-kernel testing, which is designed for ASIL B. Its next-generation EyeQ® 5 SoC for autopilot is based on the I6500-F CPU and will be manufactured with a 7nm FinFET process. EyeQ®5 is an open software platform on which customers can deploy their own algorithms - this feature is implemented through MIPS architecture technology, including hardware virtualization. Mobileye SoC is now built into a variety of ADAS systems.

"Our EyeQ® 5 SoC will be the most advanced solution for a fully autopilot that is expected to be available in 2020. The ASIL B (D) feature in the I6500-F is designed to ensure that our chips," said Elchanan Rushinek, vice president of senior engineering at Mobileye, Can achieve the highest level of security key.I6500-F in the CPU and visual accelerator between the complete cache coherency (cache coherency), making it the ideal platform for heterogeneous computing, and for the immediate function of inter-thread communication (inter- Thread communication. "Our various EyeQ® SoCs can achieve significant improvements in performance, efficiency and security, and MIPS 'multithreaded CPUs are not available."

Imagination has established a methodology and methodology for design and safety and can provide documentation in accordance with ISO 26262, including safety planning, validation review and validation measures.

The I6500-F is designed for ASIL B (D) grade requirements, making the I6500-F lockable on automotive applications with strict requirements for ASIL D rating. This IP was developed over the safety lifecycle of the Safety Element out of Context (SEooC) and worked closely with key partners, along with the independent security assessment agency ResilTech S.r.l. The design safety lifecycle of the I6500-F is closely aligned with the electronic parts 's safety lifecycle, based on ISO 26262's 2011 1st Edition standard, but has taken into account Part 11's best practices for IP, which will ISO 26262, 2nd edition, and has been published in the published DIS version

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