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積層

2017-07-06 15:10:59 | 英語特許散策

WO2016048347(特表2016-539512)
"A method to(~する方法;*不定詞の形容詞的用法)assemble low-profile and highly integrated systems for wearable device applications is described. Multiple layers of flexible thin-film substrate with embedded silicon devices interconnect(相互接続される;*自動詞)through one or more flexible interposers. The silicon devices may include central processing units, memory(*無冠詞単数), sensors and power management controllers, among others. The low-profile flexible package has one or more thin-film thermal distribution layers at the top or bottom of the packaging system.

This provides highly-integrated and low-profile wearable devices using embedded-die thin films(ダイに埋め込まれた薄膜)and flexible interposers. The thermal conditions(*初出で定冠詞;情報の受け手が、または当業者であれば、すでに分かっているはずだ、という前提だから?)for the silicon devices are improved using the thin-film thermal distribution layers. In addition, highly heterogeneous devices(*無冠詞複数;様々な不特定)may be integrated. The device and the input/output functionality may be segmented using different silicon devices and by repartitioning functional IP-blocks. The overall system is flexible to bend(曲がるように可撓性を有しており;*不定詞の副詞的用法;She is hard to work with/This is not safe to touch;判断の理由)into various locations and may be provided to market in a shorter time compared to highly complex system-on-chip (SOC) packages that have a significantly larger silicon footprint(占有面積)
When the package is bent to fit into an unconventional location, the limitations on cooling may limit the power and performance of a system such as a SoC processor. By using a molded region of a stacked(積層)die package assembly as both a package level integrated heat spreader and also an additional ground plane(接地面)to provide improved signal return paths and noise shielding of the entire package assembly, the heat can more easily be dissipated from(放熱)the silicon devices. For higher performance an additional heat sink may be coupled to the package level integrated heat spreader.

Figure 1A is a cross-sectional side view diagram of a package 101 for silicon dies that is able to accommodate(適応することができる)a variety of different form factors. The package has two layers LI, L2 to show how multiple dies may be combined into multiple layers. However, in some embodiments, one only layer LI is required. The base 102 of the package is a thermal distribution layer formed of(で形成された)a thermally conductive material such as silver or copper plating. A flexible interposer 108 is positioned between the two layers LI, L2.

The two layers are each formed of a flexible substrate 110, 112. Silicon dies are embedded into the substrate which may be formed of a variety of different materials such as a poly resin mold compound. The first layer LI is shown as having(有するように示される)a first die 104 attached to(取り付け)the flexible interposer 108 and a die stack 106 coupled to(結合)the interposer. The dies may be attached using a surface mount, ball grid, thermal compression bonding, surface activated bonding, or any other attachment approach(手法). In the die stack(積層ダイ)the lower die is attached to the upper die using pads on the lower die and through-silicon vias on the upper stack. An interposer or any other desired technique may alternatively be used to couple the two dies.

In the second layer L2, two additional dies 114, 116 are also embedded into the flexible substrate in the same way as the dies in the first layer. This allows all of die dies to be coupled to any other dies or any desired external device. In this example all of the wiring connections are through the flexible interposer that runs(延びる)between the two layers. The dies are embedded in the encapsulant layer(封止層)110, 112 so that they are held securely in place(所定の位置にしっかりと保持)and in connection with the interposer. Encapsulant layers serve as the package substrate in this example. The interposer and the encapsulant are flexible so that the package can be shaped into any desired form. The thermal distribution layer 102 is applied to(適用)one or both of the encapsulant layers to dissipate heat from the dies to the external ambient As shown it is attached to the lower layer LI. Figure IB shows a portion of the package of Figure 1A in more detail. As shown, the flexible interposer 108 may have metal routing layers配線層)142. The metal routing layers may be in one or more layers of the interposer. A dielectric material 146 may be used between the metal layers. The metal layers may include pads 148 to attach to(取り付けるためのパッド;*自動詞)contact or lands (not shown) of the dies 114 or die stacks 106, and pads to connect to(接続するためのパッド;*自動詞)vias 140. The via may be bored, etched, or drilled through the encapsulant layer to form connections for an external system or component The via may also be used to connect to the heat spreader to conduct heat from the interposer and from a die connected to the interposer to the heat spreader. The via may also have a contact that makes a connection to another part of the package when the package is folded or rolled into its final configuration as described in more detail below."

WO2014100090(特表2016-502287)
(Ab)

"An electronic assembly (100) includes horizontally-stacked(積層)die (104, 105, 106, 107) disposed at(*なぜonでなく、at?atは点的では?)an interposer (102), and may also include vertically-stacked die (107, 111, 112, 113). The stacked die are interconnected(相互接続)via a multi-hop communication network (101) that is partitioned into a link partition and a router partition. The link partition is at least partially implemented in(内に実装)the metal layers of the interposer for horizontally-stacked die. The link partition may also be implemented in part by(により実装)the intra-die interconnects (334, 335) in a single die and by the inter-die interconnects (222) connecting vertically-stacked sets of die. The router partition is implemented at(に実装)some or all of the die disposed at the interposer and comprises the logic(*初出で定冠詞;不定冠詞でもおかしくないはず)(402, 404, 406, 408) that supports the functions that route packets among the components of the processing system (100) via the interconnects of the link partition. The router partition may implement fixed routing, or alternatively may be configurable using programmable routing tables (406) or configurable logic blocks."

"The example processing system 100 includes a plurality of horizontally-stacked die 104, 105, 106, and 107 disposed at a surface of an interposer 102. The die 107 is the lowest layer of a vertical die stack 110 further including die 111, 112, and 113."

WO20070114378(特表2009-507361)
(Ab)
"A structure and a method for reduction of soft error rates in integrated circuits. The structure including: a semiconductor substrate; and a stack(積層)of one or more wiring levels stacked(積層)from a lowermost wiring level to an uppermost wiring level, the lowermost wiring level nearer the semiconductor substrate than the uppermost wiring level; and an alpha particle blocking layer on a top surface of the uppermost wiring level of the one or more wiring levels, the blocking layer comprising metal wires and a dielectric material, the blocking layer having a combination of a thickness of the blocking layer and a volume percent of metal wires in the blocking layer sufficient to(~するに十分な~)stop a predetermined percentage of alpha particles of a selected energy or less striking the blocking layer from penetrating into the stack of one or more wiring levels or the substrate."

"While the seventh, eighth(*無冠詞), ninth, tenth, eleventh and twelfth embodiments of the present invention illustrate stacking(積層)of two identical blocking layers, the two blocking layers may be different and any combination of the blocking layers of the first, second, third, fourth, fifth and sixth embodiments of the present invention may be used. Likewise(同様に), if(*する場合は;するのが前提、既定ではない)three or more blocking layers are stacked, each may independently comprise a blocking layer according to the first, second, third, fourth, fifth and sixth embodiments of the present invention.  When(*する場合;すでに話は振ってある;「その時は」)multiple blocking layers are stacked, they may or may be the same thickness(同じ厚さである;cf. have the same thickness). However, the total thickness of all blocking layers is equal to or greater than T2 (see FIG. 2). "

WO2008060256(特表2009-505442)
(Ab)
"A three-dimensional PWB is provided that may include two or more layers stacked(積層)together forming a top surface(上面), a bottom surface(下面), and one or more side surfaces(側面), and one or more solder pad situated on at least one of the one or more side surfaces. The one or more solder pads may include exposed voids in the one or more side surfaces. In some cases(一部の例では), the top surface and/or the bottom surface may have one or more solder pad. The one or more solder pads on at least one of the one or more side surfaces may be electrically connected to the one or more solder pads on the top surface and /or the bottom surface. In the illustrative PWB, the top surface and/or the bottom surface may be adapted to(適応しうる)be mounted with(が取り付けられる)an inertial sensor. The one or more side surfaces may be adapted to be mounted to(に取り付けられる)a printed wiring board."

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